TMS320DM6446_17 Datasheet, PDF (203/227 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6446
www.ti.com
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Table 6-89. Switching Characteristics Over Recommended Operating Conditions for ASP^{(1) (2)}
(see Figure 6-67)
NO.
PARAMETER
2
t_c(CKRX)
3
t_w(CKRX)
4
t_d(CKRH-FRV)
9
t_d(CKXH-FXV)
12 t_{dis(CKXH-DXHZ)}
13 t_d(CKXH-DXV)
14 t_d(FXH-DXV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
Disable time, DX high impedance following last data
bit from CLKX high
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
FSX ext
A-513,
-594,
-810
MIN
38.5 ⁽³⁾
C - 1 ⁽⁴⁾
MAX
C + 1⁽⁴⁾
-2.1
3
-1.7
3
1.7
14.4
-3.9
4
2.1
-3.9 + D1⁽⁵⁾
2.1 + D1⁽⁵⁾
-2.3 + D1⁽⁶⁾
13
4 + D2⁽⁵⁾
14.5 + D2⁽⁵⁾
4 + D2⁽⁶⁾
1.9 + D1⁽⁶⁾ 12.1 + D2⁽⁶⁾
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA3 limitations and AC timing requirements.
(4) C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency [SYSCLK1])
S = sample rate generator input clock = Not Supported if CLKSM = 0 (no CLKS pin on DM6446)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit [see footnote (3) above].
(5) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
(6) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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Peripheral and Electrical Specifications 203
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