TLC2551_16 Datasheet, PDF (5/28 Pages) Texas Instruments – 5-V, LOW-POWER, 12-BIT, 175/360 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

TLC2551, TLC2552, TLC2555
5-V, LOW-POWER, 12-BIT, 175/360 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D – MARCH 2000 – REVISED MAY 2003
control and timing (continued)
D Control via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS starts
the sampling cycle. The MSB may be read on the first falling SCLK edge after FS is low. Output data changes
on the rising edge of SCLK. This control via CS and FS is typically used for multiple devices connected to
a TMS320 DSP.
TLC2552 and TLC2555
All control is provided using CS (pin 1) on the TLC2552 and TLC2555. The cycle starts on the falling edge
transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing
is similar to the TLC2551, with control via CS only.
TLC2552 channel MUX reset cycle
The TLC2552 uses CS to reset the analog input multiplexer (MUX). A short active CS cycle (4 to 7 SCLKs) resets
the MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as is the case for a complete
conversion cycle, (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel
(see Figure 4 for timing).
sampling
The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter
has received a high-to-low CS transition (or a high-to-low FS transition for the TLC2551).
conversion
The TLC2551, TLC2552, and TLC2555 completes conversion in the following manner. The conversion starts
after the 16th SCLK falling edge during the cycle and requires 28 SCLKs to complete. Enough time for
conversion should be allowed before a rising CS or FS edge so that no conversion is terminated prematurely.
TLC2552 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0
via CS as described earlier and in Figure 4. The input is sampled for 12 SCLKs and converted. The result is
presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to
avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is not complete.
The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous
cycle.
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