TCAN1051H Datasheet, PDF (5/35 Pages) Texas Instruments – Fault Protected CAN Transceiver with CAN FD

www.ti.com
7.3 Recommended Operating Conditions
V_CC
V_IO
I_OH(RXD)
I_OL(RXD)
5-V Bus Supply Voltage Range
I/O Level-Shifting Voltage Range
RXD terminal HIGH level output current
RXD terminal LOW level output current
TCAN1051H, TCAN1051HV
TCAN1051HG, TCAN1051HGV
SLLSES8B – MARCH 2016 – REVISED MAY 2016
MIN MAX UNIT
4.5 5.5
V
2.8 5.5
–2
mA
2
7.4 Thermal Information
THERMAL METRIC⁽¹⁾
TEST CONDITIONS
R_θJA
R_θJB
R_θJC(TO
P)
Ψ_JT
Junction-to-air thermal resistance
Junction-to-board thermal resistance⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-top characterization
parameter ⁽⁵⁾
High-K thermal resistance⁽²⁾
Ψ_JB
Junction-to-board characterization
parameter ⁽⁶⁾
P_D
Average power dissipation
V_CC = 5 V, V_IO = 5 V (if applicable), T_J =
27°C, R_L = 60 Ω, S at 0 V, Input to TXD at
250 kHz, C_{L_RXD} = 15 pF. Typical CAN
operating conditions at 500 kbps with 25%
transmission (dominant) rate.
V_CC = 5.5 V, V_IO = 5.5 V (if applicable), T_J =
150°C, R_L = 50 Ω, S at 0 V, Input to TXD at
500 kHz, C_{L_RXD} = 15 pF. Typical high load
CAN operating conditions at 1 Mbps with
50% transmission (dominant) rate and
loaded network.
T_TSD Thermal shutdown temperature
T_{TSD_HY Thermal shutdown hysteresis}
S
TCAN1051
D (SOIC) DRB (VSON)
8 Pins
8 Pins
105.8
40.2
46.8
49.7
UNIT
°C/W
°C/W
48.3
15.7
°C/W
8.7
0.6
°C/W
46.2
15.9
°C/W
52
TBD
mW
124
TBD
170
TBD
°C
5
TBD
°C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, Ψ_JB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2016, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: TCAN1051H TCAN1051HV TCAN1051HG TCAN1051HGV