SN74V263-EP Datasheet, PDF (5/49 Pages) Texas Instruments – 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS695A – JUNE 2003 – REVISED JUNE 2003
Partial Reset (PRS) Master Reset (MRS)
Write Clock (WCLK)
Write Enable (WEN)
Load (LD)
(×9 or ×18) Data In (D0–Dn)
Serial Enable (SEN)
First-Word Fall-Through or Serial Input
(FWFT/SI)
Full Flag/Input Ready (FF/IR)
Programmable Almost-Full Flag (PAF)
SN74V263
SN74V273
SN74V283
SN74V293
Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
(×9 or ×18) Data Out (Q0–Qn)
Retransmit (RT)
Empty Flag/Output Ready (EF/OR)
Programmable Almost-Empty Flag (PAE)
Half-Full Flag (HF)
Big Endian/Little Endian (BE)
Interspersed/Noninterspersed Parity (IP)
Input Width
(IW)
Output Width
(OW)
Figure 1. Single-Device-Configuration Signal Flow
description/ordering information (continued)
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO
in long-word (×18) format and read out of the FIFO in small-word (×9) format. If big-endian mode is selected,
the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed
by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the
FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state
of the big-endian/little-endian (BE) pin.
The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded
into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the
FIFO assumes that the parity bit is located in bit position D8 during the parallel programming of the flag offsets.
If noninterspersed-parity mode is selected, D8 is assumed to be a valid bit and D16 and D17 are ignored. IP
mode is selected during master reset by the state of the IP input pin. This mode is relevant only when the input
width is set to ×18 mode.
The SN74V263, SN74V273, SN74V283, and SN74V293 are fabricated using TI’s high-speed submicron
CMOS technology.
For more information on this device family, see the following application reports:
D Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ External Memory Interface (EMIF)
(literature number SPRA534)
D Interfacing TI High-Speed External FIFOs With TI DSP Via DSPs’ Expansion Bus (XBus) (literature number
SPRA547)
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