SN74V263-EP Datasheet, PDF (1/49 Pages) Texas Instruments – 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V263-EP, SN74V273-EP, SN74V283-EP, SN74V293-EP
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS695A – JUNE 2003 – REVISED JUNE 2003
D Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
–55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Choice of Memory Organizations
– SN74V263 – 8192 × 18/16384 × 9
– SN74V273 – 16384 × 18/32768 × 9
– SN74V283 – 32768 × 18/65536 × 9
– SN74V293 – 65536 × 18/131072 × 9
D 133-MHz Operation
D 7.5-ns Read/Write Cycle Time
D User-Selectable Input and Output Port Bus
Sizing
– ×9 in to ×9 out
– ×9 in to ×18 out
– ×18 in to ×9 out
– ×18 in to ×18 out
D Big-Endian/Little-Endian User-Selectable
Byte Representation
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D 5-V-Tolerant Inputs
D Fixed, Low First-Word Latency
D Zero-Latency Retransmit
D Master Reset Clears Entire FIFO
D Partial Reset Clears Data, but Retains
Programmable Settings
D Empty, Full, and Half-Full Flags Signal FIFO
Status
D Programmable Almost-Empty and
Almost-Full Flags; Each Flag Can Default to
One of Eight Preselected Offsets
D Selectable Synchronous/Asynchronous
Timing Modes for Almost-Empty and
Almost-Full Flags
D Program Programmable Flags by Either
Serial or Parallel Means
D Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR and IR Flags)
D Output Enable Puts Data Outputs in
High-Impedance State
D Easily Expandable in Depth and Width
D Independent Read and Write Clocks Permit
Reading and Writing Simultaneously
D High-Performance Submicron CMOS
Technology
D Glueless Interface With ’C6x DSPs
D Available in 80-Pin Thin Quad Flat Pack
(TQFP) Package
description/ordering information
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in
first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.
ORDERING INFORMATION
TC
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TQFP (PZA)
SN74V263PZAEP V263EP
TQFP (PZA)
–55°C to 125°C
TQFP (PZA)
SN74V273PZAEP
SN74V283PZAEP
V273EP
V283EP
TQFP (PZA)
SN74V293PZAEP V293EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and}
PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2003, Texas Instruments Incorporated
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