DS90LV004_13 Datasheet, PDF (5/14 Pages) Texas Instruments – 4-Channel LVDS Buffer/Repeater with Pre-Emphasis

DS90LV004
www.ti.com
SNLS190P – APRIL 2005 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
V_CMR
Common Mode Voltage Range
V_ID = 150 mV, V_DD = 3.45V
C_IN2
Input Capacitance
IN+ or IN− to V_SS
I_IN
Input Current
V_IN = 3.45V, V_DD = V_DDMAX
V_IN = 0V, V_DD = V_DDMAX
LVDS OUTPUT DC SPECIFICATIONS (OUTn±)
V_OD
Differential Output Voltage,
0% Pre-emphasis ⁽²⁾
R_L = 100Ω external resistor between OUT+ and
OUT−
ΔV_OD
V_OS
ΔV_OS
Change in V_OD between
Complementary States
Offset Voltage ⁽³⁾
Change in V_OS between
Complementary States
I_OS
Output Short Circuit Current
C_OUT2 Output Capacitance
SUPPLY CURRENT (Static)
OUT+ or OUT− Short to GND
OUT+ or OUT− to GND when TRI-STATE^®
I_CC
Supply Current
All inputs and outputs enabled and active,
terminated with differential load of 100Ω between
OUT+ and OUT-, 0% pre-emphasis
I_CCZ
Supply Current - Power Down
PWDN = L, 0% pre-emphasis
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200 Mbps,
Time
measure between 20% and 80% of V_OD. ⁽⁴⁾
t_HLT
Differential High to Low Transition
Time
t_PLHD
t_PHLD
t_SKD1
t_SKCC
t_SKP
t_JIT
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew
Output Channel to Channel Skew
Part to Part Skew
Jitter (0% Pre-emphasis)
(5)
Use an alternating 1 and 0 pattern at 200 Mbps,
measure at 50% V_OD between input to output.
|t_PLHD–t_PHLD| ⁽⁴⁾
Difference in propagation delay (t_PLHD or t_PHLD)
among all output channels. ⁽⁴⁾
Common Edge, parts at same temp and V_CC(4)
RJ - Alternating 1 and 0 at 750 MHz ⁽⁶⁾
DJ - K28.5 Pattern, 1.5 Gbps ⁽⁷⁾
TJ - PRBS 2²³-1 Pattern, 1.5 Gbps ⁽⁸⁾
t_ON
LVDS Output Enable Time
Time from PWDN to OUT± change from TRI-STATE
to active.
t_OFF
LVDS Output Disable Time
Time from PWDN to OUT± change from active to
TRI-STATE.
Min
0.05
−10
−10
250
−35
1.05
−35
Typ
(1)
Max Units
3.40
V
3.5
pF
+10
µA
+10
µA
500
600
mV
35
mV
1.18 1.475
V
35
mV
−60
−90
mA
5.5
pF
117
140
mA
2.7
6
mA
210
300
ps
210
300
ps
2.0
3.2
ns
2.0
3.2
ns
25
80
ps
50
125
ps
1.1
ns
1.1
1.5 psrms
43
62 psp-p
35
85 psp-p
300
ns
12
ns
(3) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5) Jitter is not production tested, but ensured through characterization on a sample basis.
(6) Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50%
duty cycle at 750MHz, t_r = t_f = 50ps (20% to 80%).
(7) Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = V_ID = 500mV, K28.5
pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
(8) Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been
subtracted. The input voltage = V_ID = 500mV, 2²³-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%).
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