DS90CR211MTDX Datasheet, PDF (5/15 Pages) Texas Instruments – DS90CR211/DS90CR212 21-Bit Channel Link

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
RECEIVER SUPPLY CURRENT
I_CCRZ
Receiver Supply Current,
Power Down
Conditions
Power Down = Low
Min
Typ
Max Units
1
10
µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 5.0V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V_OD).
Note 4: ESD Rating:
HBM (1.5 kΩ, 100 pF)
PLL V _CC ≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
Parameter
LVDS Low-to-High Transition Time (Figure 2)
LVDS High-to-Low Transition Time (Figure 2)
TxCLK IN Transition Time (Figure 4)
TxOUT Channel-to-Channel Skew (Note 5) (Figure 5)
Transmitter Output Pulse Position for Bit0 (Figure 16)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
f = 20 MHz
TPPos6
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
Transmitter Output Pulse Position for Bit6
Transmitter Output Pulse Position for Bit0 (Figure 16)
Transmitter Output Pulse Position for Bit1
Transmitter Output Pulse Position for Bit2
Transmitter Output Pulse Position for Bit3
Transmitter Output Pulse Position for Bit4
Transmitter Output Pulse Position for Bit5
Transmitter Output Pulse Position for Bit6
TxCLK IN Period (Figure 6)
TxCLK IN High Time (Figure 6)
TxCLK IN Low Time (Figure 6)
TxIN Setup to TxCLK IN (Figure 6)
THTC
TCCD
TPLLS
TPDD
TxIN Hold to TxCLK IN (Figure 6)
TxCLK IN to TxCLK OUT Delay @ 25˚C, V_CC = 5.0V (Figure 8)
Transmitter Phase Lock Loop Set (Figure 10)
Transmitter Powerdown Delay (Figure 14)
f = 40 MHz
f = 20 MHz
f = 40 MHz
Note 5: This limit based on bench characterization.
Min
−200
6.3
12.8
20
27.2
34.5
42.2
−100
2.9
6.1
9.7
13
17
20.3
25
0.35T
0.35T
14
8
2.5
5
Typ
0.75
0.75
150
7.2
13.6
20.8
28
35.2
42.6
100
3.3
6.6
10.2
13.5
17.4
20.8
T
0.5T
0.5T
2
Max
1.5
1.5
8
350
350
7.5
14.6
21.5
28.5
35.6
42.9
300
3.9
7.1
10.7
14.1
17.8
21.4
50
0.65T
0.65T
9.7
10
100
Units
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
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