DS90CR211MTDX Datasheet, PDF (12/15 Pages) Texas Instruments – DS90CR211/DS90CR212 21-Bit Channel Link

Applications Information (Continued)
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
FIGURE 18. LVDS Serialized Link Termination
DS012637-20
UNUSED INPUTS: All unused inputs at the TxW inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each V_CC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V_CC should receive
the most filtering/bypassing. Next would be the LVDS V_CC
pins and finally the logic V_CC pins.
DS012637-21
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLL to generate and recover the clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
40 MHz clock has a period of 25 ns which results in a data bit
width of 3.57 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to an-
other) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noise signal. Individual bypassing of each V_CC to ground
will minimize the noise passed on to the PLL, thus creating a
low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
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