DS90C365A_13 Datasheet, PDF (5/17 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

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AC Timing Diagrams
DS90C365A
SNLS181I – APRIL 2004 – REVISED APRIL 2013
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
B. Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Figure 1. “Worst Case” Test Pattern
A. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
B. Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
C. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 2. “16 Grayscale” Test Pattern - DS90C365A
Figure 3. DS90C365A (Transmitter) LVDS Output Load. 5pF is showed as board loading
Figure 4. DS90C365A (Transmitter) LVDS Transition Times
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