DLP9500UV Datasheet, PDF (5/54 Pages) Texas Instruments – LVDS Type A DMD

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DLP9500UV
DLPS033B – NOVEMBER 2014 – REVISED JUNE 2015
PIN ⁽¹⁾
NAME
NO.
D_AP(11)
H14
D_AP(12)
D16
D_AP(13)
F16
D_AP(14)
C15
D_AP(15)
G17
DATA BUS B
D_BN(0)
AH2
D_BN(1)
AD8
D_BN(2)
AJ5
D_BN(3)
AE3
D_BN(4)
AG9
D_BN(5)
AE11
D_BN(6)
AH10
D_BN(7)
AF10
D_BN(8)
AK8
D_BN(9)
AG5
D_BN(10)
AL11
D_BN(11)
AE15
D_BN(12)
AH14
D_BN(13)
AF14
D_BN(14)
AJ17
D_BN(15)
AD16
D_BP(0)
AH4
D_BP(1)
AD10
D_BP(2)
AJ3
D_BP(3)
AE5
D_BP(4)
AG11
D_BP(5)
AE9
D_BP(6)
AH8
D_BP(7)
AF8
D_BP(8)
AK10
Pin Functions (continued)
TYPE
(I/O/P)
SIGNAL
Input
LVCMOS
Input
LVCMOS
Input
LVCMOS
Input
LVCMOS
Input
LVCMOS
DATA
RATE ⁽²⁾
INTERNAL
TERM ⁽³⁾
CLOCK
DDR
DDR
DDR
DDR
DDR
Differentially
terminated – 100 Ω
DCLK_A
Differentially
terminated – 100 Ω
DCLK_A
Differentially
terminated – 100 Ω
DCLK_A
Differentially
terminated – 100 Ω
DCLK_A
Differentially
terminated – 100 Ω
DCLK_A
DESCRIPTION
Input data bus A
(2x LVDS)
TRACE
(MILS)
71.7
198.69
143.72
240.14
74.05
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Differentially
terminated – 100 Ω
DCLK_B
Input data bus B
(2x LVDS)
525.25
190.59
525.25
494.91
222.67
205.45
309.05
285.62
483.58
711.58
462.21
74.39
194.26
156
247.9
111.52
525.02
190.61
524.22
476.07
222.8
219.48
306.55
298.04
480.31
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