CDC509_15 Datasheet, PDF (5/13 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC509
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
ą
SCAS576C − JULY 1996 − REVISED DECEMBER 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Note 5 and Figures 1 and 2)^†
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.165 V
MIN TYP MAX
VCC = 3.3 V
± 0.3 V
MIN
TYP MAX
UNIT
tphase _error, reference
(see Figure 3)
66 MHz < CLKIN↑ < 100
MHz
FBIN↑
100...480
ps
tphase _error, − jitter,
(see Note 6)
tsk(o)‡
Jitter(pk-pk)
Duty cycle, reference
(see Figure 4)
CLKIN↑ = 100 MHz
Any Y or FBOUT
F(clkin > 66 MHz)
F(clkin ≤ 66 MHz)
F(clkin > 66 MHz)
FBIN↑
220
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
480
−100
45%
43%
340
ps
200 ps
100 ps
55%
57%
tr
Any Y or FBOUT
1.1 1.5 0.7
1.6 ns
tf
Any Y or FBOUT
0.8 1.3 0.5
1.5 ns
† _{This parameters are not production tested.}
‡ _{The tsk(o) specification is only valid for equal loading of all outputs.}
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% VCC range.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
500 W
Input
tpd
50% VCC
Output
2V
0.4 V
tr
2V
50% VCC
tf
3V
0V
VOH
0.4 V
VOL
LOAD CIRCUIT FOR OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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