CDC509_15 Datasheet, PDF (4/13 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC509
3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER
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SCAS576C − JULY 1996 − REVISED DECEMBER 2004
recommended operating conditions (see Note 4)
VCC Supply voltage
VIH High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
IOH High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
MIN MAX UNIT
3 3.6 V
2
V
0.8 V
0 VCC V
−20 mA
20 mA
0
70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP†
VIK
II = −18 mA
3V
VOH
IOH = −100 µA
IOH = −20 mA
MIN to MAX VCC−0.2
3V
2.4
VOL
IOL = 100 µA
IOL = 20 mA
MIN to MAX
3V
II
ICC‡
VI = VCC or GND
VI = VCC or GND,
IO = 0, Outptus high or low
3.6 V
3.6 V
∆ICC
One input at VCC − 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V
Ci
VI = VCC or GND
3.3 V
4
Co
VO = VCC or GND
3.3 V
6
† _{For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.}
‡ _{For ICC of AVCC, see Figure 5.}
MAX
−1.2
0.2
0.55
±5
10
500
UNIT
V
V
V
µA
µA
µA
pF
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
fclock Clock frequency
25 125 MHz
Input clock duty cycle
40% 60%
Stabilization time§
1 ms
§ _{Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a}
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
4
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