CDC328A_09 Datasheet, PDF (5/7 Pages) Texas Instruments – 1Line to 6Line Clock Driver

CDC328A
1ĆLINE TO 6ĆLINE CLOCK DRIVER
WITH SELECTABLE POLARITY
SCAS327B − DECEMBER 1992 − REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR OUTPUTS
Input
(see Note B)
tPLH
1.5 V
1.5 V
3V
0V
tPHL
Output
1.5 V
0.8 V
tr
2V
VOH
1.5 V
0.8 V _VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
5