BQ76PL455A-Q1 Datasheet, PDF (5/130 Pages) Texas Instruments – 16-Cell EV/HEV Integrated Battery Monitor and Protector

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NAME
PIN
NO.
FAULTH+
57
FAULTL–
51
FAULTL+
50
GPIO0
47
GPIO1
46
GPIO2
45
GPIO3
44
GPIO4
43
GPIO5
42
NC1
36
NC2
75
NPNB
71
OUT1
73
OUT2
68
RX
39
TOP
76
TX
38
V5VAO
58
VDIG
34
VIO
41
VM
31
bq76PL455A-Q1
SLUSC51B – APRIL 2015 – REVISED DECEMBER 2015
Pin Functions (continued)
TYPE⁽¹⁾
DESCRIPTION
Non-inverting, high-side differential connection to the FAULTL+ pin of the higher adjacent module in
DI
a daisy chain.
Leave this pin unconnected if not used.
Inverting, low-side differential connection to the FAULTH– pin of the lower adjacent module in a
DO daisy chain.
Leave this pin unconnected if not used.
Non-inverting, low-side differential connection to the FAULTH+ pin of the lower adjacent module in a
DO daisy chain.
Leave this pin unconnected if not used.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input or address assignment.
Do not allow GPIO pins to float when configured as inputs.
DIO
General Purpose I/O. Optionally use this pin as an external FAULT input.
Do not allow GPIO pins to float when configured as inputs.
NC Do not connect to this pin. This pin must remain floating for correct operation.
NC Do not connect to this pin. This pin must remain floating for correct operation.
AO
Internal voltage regulator controller output pin. Connect to the base of the external NPN transistor.
Leave unconnected if not used.
AO
Analog multiplexer output. Connect a 390-pF filter capacitor type C0G or NP0 between this pin and
AGND. Connect externally to pin OUT2. Internally tied to pin OUT2.
AI
ADC input pin. Connect externally to pin OUT1. Internally tied to pin OUT1.
Single-ended UART receive input. This pin must be either:
DI
• Driven from a UART signal OR
• Pulled up to VIO
Do not allow this pin to float at any time.
Power supply input and module voltage-measurement pin. Connect to the top cell of the module
through a series resistor. Requires a decoupling capacitor⁽³⁾ from TOP to the ground plane. See
P
TOP Pin Connection for details. Locate decoupling capacitor as close to pin as possible. The low-
pass filter created by the RC should have a tau similar to the low-pass filter used in the VSENSE
circuits. See VP Regulated Output or Application and Implementation for component selection
details.
DO Single-ended UART transmit output. Leave this pin unconnected if not used.
Connection to internal 5-V always-on supply. Decouple with a 4.7-µF capacitor⁽³⁾ connected to the
P
ground plane. Locate decoupling capacitor as close to pin as possible. This pin should not be used
to supply external circuitry.
5.3-V Digital Supply input. Always connect VDIG to VP with 1-Ω resistor. Decouple with 4.7-µF and
P
0.1-µF capacitors⁽³⁾ in parallel to the ground plane. Locate decoupling capacitors as close to the
VDIG pin as possible.
3-V to 5-V power input for IO supply. Connect this pin to the same power supply used to drive the
source/receiver for the GPIO, FAULT_N, RX, and TX pins. Typically, connect this pin to VP/VDIG
for all devices except the base device in the stack. In the base (or single) device, this pin is typically
P
driven from the same supply as the microcontroller I/O pins.
If VP/VDIG is connected as the power source, this pin should be decoupled with a 0.1-µF
capacitor⁽³⁾ to the digital ground plane. Place a 1-Ω resistor in series from VP to VIO. Locate the
decoupling capacitor as close to the VIO pin as possible.
If another supply is used, decouple with parallel 10-µF and 0.1-µF capacitors⁽³⁾.
P
Internal –5-V charge pump output. Decouple with 4.7-µF and 0.1-µF capacitors⁽³⁾ in parallel to the
ground plane. Locate decoupling capacitor as close to pin as possible.
Copyright © 2015, Texas Instruments Incorporated
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