BQ29311_15 Datasheet, PDF (5/24 Pages) Texas Instruments – FOUR-CELL LITHIUM-ION

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Not Recommended for New Designs
bq29311
SLUS487D − DECEMBER 2001 − REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS CONTINUED
TA = 25°C, CREG = 1 µF, VCC = 14 V (unless otherwise noted)
AC
f(CLKIN)
t(CLKIN_HI)
f(INTERNAL)
PARAMETER
CLKIN input frequency
CLKIN high time
Internal clock frequency
t(SCDDELAY) SC delay time
TEST CONDITIONS
External clock
External clock
TA = − 25°C to 85°C
td(SC) = 0 ms for charge and discharge
V(OCD) = 100 mV, SR(50%) to DSG/CHG(50%) delay.
No load.
MIN TYP MAX
32.100 32.768 33.420
2
28
26.2 32.768 39.4
1
10
UNIT
kHz
µs
kHz
µs
Terminal Functions
TERMINAL
NAME
NO.
CHG
21
CLKIN
16
CNTL
10
DSG
23
GND
11, 13
LEDOUT
20
PCHG
22
SCLK
14
SDATA
15
SR1
8
SR2
9
TOUT
18
VBAT
2
VC1
3
VC2
4
VC3
5
VC4
6
VC5
7
VCC
1
VCELL
12
VPACK
24
VREG
19
XALERT
17
DESCRIPTION
Push-pull output charge FET gate voltage supply
Digital input that provides an alternate clock with internal 100-kΩ pullup to VREG
Active low input enables CHG, DSG and PCHG. Internal pullup
Push-pull output discharge FET gate voltage supply
Analog ground pin and negative pack terminal
Provides current to drive LED capacity display
Push-pull output precharge FET gate voltage supply
Open-drain bidirectional serial interface clock with internal 10-kΩ pullup to VREG
Open-drain bidirectional serial interface data with internal 10-kΩ pullup to VREG
Current sense positive terminal when charging relative to SR2
Current sense positive terminal when discharging relative to SR1
Provides thermistor bias current
Battery positive terminal sense input for regulator shutdown
Sense voltage input terminal for most positive cell and balance current input for most positive cell. Connected to VC2 in 3-cell
applications
Sense voltage input terminal for second most positive cell, balance current input for second most positive cell, and return
balance current for most positive cell
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return balance
current for second most positive cell
Sense voltage input terminal for least positive cell, balance current input for least positive cell, and return balance current
for third most positive cell
Sense voltage input terminal for most negative cell, return balance current for least positive cell
Diode protected BAT+ terminal and primary power source
Output of scaled value of the measured cell voltage
Pack positive terminal and alternate power source
Integrated 3.3-V regulator output
Open-drain output used to indicate status register changes. With internal 100 kΩ pullup to VREG
5