ADC124S021 Datasheet, PDF (5/27 Pages) National Semiconductor (TI) – 4 Channel, 200 kSPS, 12-Bit A/D Converter

ADC124S021
www.ti.com
SNAS277F – MARCH 2005 – REVISED MARCH 2013
ADC124S021 Converter Electrical Characteristics ⁽¹⁾ (continued)
The following specifications apply for V_A = +2.7V to 5.25V, GND = 0V, f_SCLK = 0.8 MHz to 3.2 MHz, f_SAMPLE = 50 ksps to 200
ksps, C_L = 35 pF, unless otherwise noted. Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical
Limits ⁽²⁾
Units
C_OUT
TRI-STATE® Output Capacitance
Output Coding
2
4
pF (max)
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C_L = 10 pF)
V_A
Supply Voltage
2.7
V (min)
5.25
V (max)
Supply Current, Normal Mode
(Operational, CS low)
I_A
Supply Current, Shutdown (CS high)
Power Consumption, Normal Mode
(Operational, CS low)
P_D
Power Consumption, Shutdown (CS
high)
AC ELECTRICAL CHARACTERISTICS
V_A = +5.25V
f_SAMPLE = 200 ksps, f_IN = 39.9 kHz
V_A = +3.6V,
f_SAMPLE = 200 ksps, f_IN = 39.9 kHz
V_A = +5.25V
f_SAMPLE = 0 ksps
V_A = +3.6V,
f_SAMPLE = 0 ksps
V_A = +5.25V
V_A = +3.6V,
V_A = +5.25V
V_A = +3.6V,
1.5
2.1
mA (max)
0.62
1.0
mA (max)
60
nA
38
nA
7.9
11.0
mW (max)
2.2
3.6
mW (max)
0.32
µW
0.14
µW
f_SCLK
Maximum Clock Frequency
(3)
0.8
MHz (min)
3.2
MHz (max)
f_S
Sample Rate
(3)
50
ksps (min)
200
ksps (max)
t_CONV
DC
Conversion Time
SCLK Duty Cycle
f_SCLK = 3.2 MHz
13
SCLK cycles
30
% (min)
50
70
% (max)
t_ACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
Acquisition Time + Conversion Time
3
SCLK cycles
16
SCLK cycles
(3) This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is
specified under Operating Ratings.
ADC124S021 Timing Specifications
The following specifications apply for V_A = +2.7V to 5.25V, GND = 0V, f_SCLK = 0.8 MHz to 3.2 MHz, f_SAMPLE = 50 ksps to 200
ksps, C_L = 35 pF, Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25°C.
Symbol
Parameter
Conditions
Typical Limits ⁽¹⁾ Units
t_CSU Setup Time SCLK High to CS Falling Edge
(2)
t_CLH Hold time SCLK Low to CS Falling Edge
(2)
t_EN Delay from CS Until DOUT active
t_ACC Data Access Time after SCLK Falling Edge
t_SU Data Setup Time Prior to SCLK Rising Edge
t_H
Data Valid SCLK Hold Time
t_CH SCLK High Pulse Width
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
V_A = +3.0V
V_A = +5.0V
−3.5
10
ns (min)
−0.5
+4.5
10
ns (min)
+1.5
+4
30
ns (max)
+2
+14.5
+13
30
ns (max)
+3
10
ns (min)
+3
10
ns (min)
0.5 x t_SCLK 0.3 x t_SCLK ns (min)
(1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(2) Clock may be either high or low when CS is asserted as long as setup and hold times t_CSU and t_CLH are strictly observed.
Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: ADC124S021