ADC124S021 Datasheet, PDF (16/27 Pages) National Semiconductor (TI) – 4 Channel, 200 kSPS, 12-Bit A/D Converter

ADC124S021
SNAS277F – MARCH 2005 – REVISED MARCH 2013
APPLICATIONS INFORMATION
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1.0 ADC124S021 OPERATION
The ADC124S021 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Simplified schematics of the ADC124S021 in both track and hold modes
are shown in Figure 46, and Figure 47, respectively. In Figure 46, the ADC124S021 is in track mode: switch
SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2
balances the comparator inputs. The ADC124S021 is in this state for the first three SCLK cycles after CS is
brought low.
Figure 47 shows the ADC124S021 in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The ADC124S021 is in this state for the fourth through sixteenth SCLK cycles after CS
is brought low.
The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of
16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is
clocked into the DIN pin to indicate the multiplexer address for the next conversion.
IN1
MUX
IN4
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A
2
Figure 46. ADC124S021 in Track Mode
IN1
MUX
IN4
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A
2
Figure 47. ADC124S021 in Hold Mode
2.0 USING THE ADC124S021
Figure 2 and Figure 4 for the ADC124S021 are shown in Timing Diagrams. CS is chip select, which initiates
conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and
the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data
stream, MSB first. Data to be written to the ADC124S021's Control Register is placed on DIN, the serial data
input pin. New data is written to the ADC at DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when
CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a
power down state when CS is high, and also between continuous conversion cycles.
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