ADC10731_14 Datasheet, PDF (5/34 Pages) Texas Instruments – 10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference

ADC10731, ADC10732, ADC10734, ADC10738
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SNAS081D – MAY 1999 – REVISED MARCH 2013
Electrical Characteristics
The following specifications apply for V⁺ = AV⁺ = DV⁺ = +5.0 V_DC, V_REF+ = 2.5 V_DC, V_REF− = GND, V_IN− = 2.5V for Signed
Characteristics, V_IN− = GND for Unsigned Characteristics and f_CLK = 2.5 MHz unless otherwise specified. Boldface limits
apply for T_A = T_J = T_MIN to T_MAX; all other limits T_A = T_J = +25°C.^(1)(2)(3)(4)
Parameter
Test Conditions
Typ ⁽⁵⁾
Limits ⁽⁶⁾
Units
(Limits)
SIGNED STATIC CONVERTER CHARACTERISTICS
TUE
Resolution with No Missing Codes
Total Unadjusted Error⁽⁷⁾
10 + Sign
Bits
±2.0
LSB (max)
INL
Positive and Negative Integral Linearity Error
±1.25
LSB (max)
Positive and Negative Full-Scale Error
±1.5
LSB (max)
Offset Error
±1.5
LSB (max)
Power Supply Sensitivity
Offset Error
+ Full-Scale Error
±0.2
±1.0
LSB (max)
V⁺ = +5.0V ±10%
±0.2
±1.0
LSB (max)
− Full-Scale Error
±0.1
±0.75
LSB (max)
DC Common Mode Error⁽⁸⁾
Multiplexer Chan to Chan Matching
V_IN+ = V_IN− = V_IN where
5.0V ≥ V_IN ≥ 0V
±0.1
±0.1
±0.33
LSB (max)
LSB
UNSIGNED STATIC CONVERTER CHARACTERISTICS
TUE
INL
Resolution with No Missing Codes
Total Unadjusted Error⁽⁷⁾
Integral Linearity Error
Full-Scale Error
Offset Error
Power Supply Sensitivity
Offset Error
Full-Scale Error
DC Common Mode Error⁽⁸⁾
Multiplexer Channel to Channel Matching
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
V_REF+ = 4.096V
V_REF+ = 4.096V
V_REF+ = 4.096V
V_REF+ = 4.096V
V⁺ = +5.0V ±10%
V_REF+ = 4.096V
V_IN+ = V_IN− = V_IN where
+5.0V ≥ V_IN ≥ 0V
V_REF+ = 4.096V
±0.75
±0.50
±0.1
±0.1
±0.1
±0.1
10
±1.25
±1.25
Bits
LSB
LSB
LSB (max)
LSB (max)
LSB
LSB
LSB
LSB
S/(N+D) Signal-to-Noise Plus Distortion Ratio
V_IN = 4.85 V_PP, and
f_IN = 1 kHz to 15 kHz
67
dB
ENOB Effective Number of Bits
V_IN = 4.85 V_PP, and
f_IN = 1 kHz to 15 kHz
10.8
Bits
THD
Total Harmonic Distortion
V_IN = 4.85 V_PP, and
f_IN = 1 kHz to 15 kHz
−78
dB
IMD
Intermodulation Distortion
V_IN = 4.85 V_PP, and
f_IN = 1 kHz to 15 kHz
−85
dB
Full-Power Bandwidth
V_IN = 4.85 V_PP, where
S/(N + D) Decreases 3 dB
380
kHz
Multiplexer Chan to Chan Crosstalk
f_IN = 15 kHz
−80
dB
(1) Two on-chip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop
below ground or one diode drop greater than V⁺ supply. Be careful during testing at low V⁺ levels (+4.5V), as high level analog inputs
(+5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors In the conversion result. The
specification allows 50 mV forward bias of either diode; this means that as long as the analog V_IN does not exceed the supply voltage by
more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected
channel. If AV⁺ and DV⁺ are minimum (4.5 V_DC) and full scale must be ≤+4.55 V_DC. See Figure 6
(2) No connection exists between AV⁺ and DV⁺ on the chip.To ensure accuracy, it is required that the AV⁺ and DV⁺ be connected together
to a power supply with separate bypass filter at each V⁺ pin.
(3) One LSB is referenced to 10 bits of resolution.
(4) All the timing specifications are tested at the TTL logic levels, V_IL = 0.8V for a falling edge and V_IH = 2.0V for a rising. TRl-STATE
voltage level is forced to 1.4V.
(5) Typicals are at T_J = T_A = 25°C and represent most likely parametric norm.
(6) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
(7) Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
(8) The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels
shorted together.
Copyright © 1999–2013, Texas Instruments Incorporated
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