ADC08L060_14 Datasheet, PDF (5/29 Pages) Texas Instruments – 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal Sample-and-Hold

ADC08L060
www.ti.com
SNAS167G – MAY 2002 – REVISED MARCH 2013
Converter Electrical Characteristics
The following specifications apply for V_A = V_DR = +3.0V_DC, V_RT = +1.9V, V_RB = 0.3V, C_L = 10 pF, f_CLK = 60 MHz at 50% duty
cycle. Boldface limits apply for T_J = T_MIN to T_MAX: all other limits T_J = 25°C ^{(1)(2) (3)}
Symbol
Parameter
Conditions
Typical
(4)
Limits
(4)
Units
(Limits)
DC ACCURACY
INL
Integral Non-Linearity
+0.5
−0.2
+1.9
−1.35
LSB (max)
LSB (min)
DNL
Differential Non-Linearity
±0.25
±0.90
LSB (max)
Missing Codes
0
(max)
FSE
Full Scale Error
3.0
±13
mV (max)
V_OFF
Zero Scale Offset Error
ANALOG INPUT AND REFERENCE CHARACTERISTICS
19
27
mV (max)
V_IN
Input Voltage
C_IN
V_IN Input Capacitance
1.6
V_RB
V (min)
V_RT
V (max)
(CLK LOW)
3
pF
V_IN = 0.75V +0.5 Vrms _{(CLK HIGH)}
4
pF
R_IN
R_IN Input Resistance
BW
Full Power Bandwidth
>1
MΩ
270
MHz
V_RT
Top Reference Voltage
1.9
V_A
V (max)
0.5
V (min)
V_RB
Bottom Reference Voltage
0.3
V_RT − 0.5
V (max)
0
V (min)
V_RT - V_RB Reference Delta
2.3
V (max)
1.6
1.0
V (min)
R_REF
Reference Ladder Resistance
V_RT to V_RB
590
Ω (min)
720
1070
Ω (max)
I_ref
Reference Ladder Current
V_RT to V_RB
1.5
mA (min)
2.2
2.7
mA (max)
(1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only
and are not ensured.
(2) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above V_DR or below GND by more than 100 mV.
For example, if V_A is 2.7V_DC the full-scale input voltage must be ≤2.8V_DC to ensure accurate conversions.
(3) To ensure accuracy, it is required that V_A and V_DR be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(4) Typical figures are at T_J = 25°C, and represent most likely parametric norms at specific conditions at the time of product characterization
and are not ensured. Test limits are specifid to TI's AOQL (Average Outgoing Quality Level).
Copyright © 2002–2013, Texas Instruments Incorporated
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