74AC11874 Datasheet, PDF (5/7 Pages) Texas Instruments – DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

74AC11874
DUAL 4ĆBIT DĆTYPE EDGEĆTRIGGERED FLIPĆFLOP
WITH 3ĆSTATE OUTPUTS
SCAS236 − MARCH 1990 − REVISED APRIL 1993
operating characteristics, V_CC = 5 V, T_A = 25°C
PARAMETER
Cpd
Power dissipation capacitance per flip-flop
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
31
pF
13
From Output
Under Test
CL = 50 pF
(see Note A)
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
2 × VCC
S1
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
GND
Timing Input
Data Input
Input
(see Note B)
tPLH
Output
(see Note D)
LOAD CIRCUIT FOR OUTPUTS
50%
tsu
th
50%
50%
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
0V
VCC
0V
50%
50%
VCC
0V
tPHL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tw
Input 50%
50%
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
0V
Output
Control
(low-level
enabling)
tPZL
50%
50%
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPZH
Output
Waveform 2
S1 at GND
(see Note C)
50% VCC
tPHZ
20% VCC
50% VCC
80% VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC
0V
≈ VCC
VOL
VOH
0V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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