74AC11874 Datasheet, PDF (4/7 Pages) Texas Instruments – DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

74AC11874
DUAL 4ĆBIT DĆTYPE EDGEĆTRIGGERED FLIPĆFLOP
WITH 3ĆSTATE OUTPUTS
SCAS236 − MARCH 1990 − REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V_CC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
fclock
tw
Clock frequency
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
CLR low
CLK high or low
Data
CLR inactive
Data
TA = 25°C
MIN MAX
0
60
4
8.3
3
1.5
1
MIN MAX UNIT
0
60 MHz
4
ns
8.3
3
ns
1.5
1
ns
timing requirements over recommended operating free-air temperature range, V_CC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
fclock
tw
Clock frequency
Pulse duration
tsu
Setup time before CLK↑
th
Hold time after CLK↑
CLR low
CLK high or low
Data
CLR inactive
Data
TA = 25°C
MIN MAX
0 125
4
4
2
1.5
1
MIN MAX UNIT
0 125 MHz
4
ns
4
2
ns
1.5
1
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MIN TYP MAX
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
CLR
OE
OE
60
60
2.9 7.3
11 2.9
Q
3.7 8.8 13.1 3.7
Q
3.9 9.3
14 3.9
2.1 5.6 8.7 2.1
Q
3.1 8.4 13.1 3.1
4 6.2 8.2
4
Q
3.9 6.3 8.5 3.9
MAX
12.5
14.6
15.7
9.8
14.9
8.7
9
UNIT
MHz
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V_CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MIN TYP MAX
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
CLR
OE
OE
125
125
2.3 5.2 7.4 2.3
Q
2.9 6.1 8.6 2.9
Q
2.9 6.3 8.9 2.9
1.5
4 5.9 1.5
Q
2.3 5.4 7.8 2.3
3.8 5.7 7.3 3.8
Q
3.7 5.5 7.1 3.7
MAX
8.3
9.6
10
6.6
8.8
7.7
7.5
UNIT
MHz
ns
ns
ns
ns
4
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