LM3S1R21 Datasheet, PDF (496/947 Pages) Texas Instruments – Stellaris® LM3S1R21 Microcontroller

External Peripheral Interface (EPI)
Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIGPCFG, the MODE field must be 0x0.
The RD2CYC bit must be set at all times in General-Purpose mode to ensure proper
operation.
The General-Purpose configuration register is used to configure the control, data, and address pins.
This mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition
and actuator control. Note that this register is reset when the MODE field in the EPICFG register is
changed. If another mode is selected and the General-purpose mode is selected again, the register
the values must be reinitialized.
This mode is designed for 3 general types of use:
■ Extremely high-speed clocked interfaces to FPGAs and CPLDs, with 3 sizes of data and optional
address. Framing and clock-enable permit more optimized interfaces.
■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely
controlled by the baud rate in the EPIBAUD register (when used with the NBRFIFO and/or the
WFIFO) or by rate of accesses from software or μDMA.
■ General custom interfaces of any speed.
The configuration allows for choice of an output clock (free running or gated), a framing signal (with
frame size), a ready input (to stretch transactions), read and write strobes, address of varying sizes,
and data of varying sizes. Additionally, provisions are made for splitting address and data phases
on the external interface.
EPI General-Purpose Configuration (EPIGPCFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
CLKPIN CLKGATE reserved RDYEN FRMPIN FRM50
Type R/W
R/W
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
MAXWAIT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
24
23
22
FRMCNT
R/W
R/W
R/W
0
0
0
8
7
6
reserved
R/W
RO
RO
0
0
0
21
RW
R/W
0
20
19
18
reserved WR2CYC RD2CYC
RO
R/W
R/W
0
0
0
17
16
reserved
RO
RO
0
0
5
4
ASIZE
R/W
R/W
0
0
3
2
reserved
RO
RO
0
0
1
0
DSIZE
R/W
R/W
0
0
Bit/Field
31
Name
CLKPIN
Type
R/W
Reset
0
Description
Clock Pin
Value Description
0 No clock output.
1 EPI0S31 functions as the EPI clock output.
The EPI clock is generated from the COUNT0 field in the EPIBAUD
register (as is the system clock which is divided down from it).
496
January 21, 2012
Texas Instruments-Production Data