LM3S5662 Datasheet, PDF (495/841 Pages) Texas Instruments – Stellaris® LM3S5662 Microcontroller

Stellaris® LM3S5662 Microcontroller
for each zero. On the reception side, the incoming light pulses energize the photo transistor base
of the receiver, pulling its output LOW. This drives the UART input pin LOW.
■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the
period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz
frequency) by changing the appropriate bit in the UARTCR register. See page 506 for more
information on IrDA low-power pulse-duration configuration.
Figure 13-3 on page 495 shows the UART transmit and receive signals, with and without IrDA
modulation.
Figure 13-3. IrDA Data Modulation
UnTx
Start
bit
0
1
Data bits
0
1
0
0
1
1
Stop
bit
0
1
UnTx with IrDA
UnRx with IrDA
Bit period
3
16
Bit period
UnRx
0
1
Start
0
1
0
0
Data bits
1
1
0
1
Stop
13.3.5
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal
as an alternate function must be configured as the UnRx signal and pulled High.
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 500). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 509).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 504) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
November 17, 2011
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