LM3S9D81 Datasheet, PDF (493/1277 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex

Stellaris^® LM3S9D81 Microcontroller
Bit/Field
7:6
5:4
3
2
Name
WRWS
RDWS
reserved
BSEL
Type
R/W
R/W
RO
R/W
Reset
0x0
0x0
0
0
Description
Write Wait States
This field adds wait states to the data phase of CS0n (the address phase
is not affected). The effect is to delay the rising edge of WRn (or the
falling edge of WR). Each wait state adds 2 EPI clock cycles to the
access time.
Value Description
0x0 Active WRn is 2 EPI clocks.
0x1 Active WRn is 4 EPI clocks.
0x2 Active WRn is 6 EPI clocks.
0x3 Active WRn is 8 EPI clocks.
This field is used in conjunction with the EPIBAUD register.
Read Wait States
This field adds wait states to the data phase of CS0n (the address phase
is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state adds 2 EPI clock cycles to the access time.
Value Description
0x0 Active RDn is 2 EPI clocks.
0x1 Active RDn is 4 EPI clocks.
0x2 Active RDn is 6 EPI clocks.
0x3 Active RDn is 8 EPI clocks.
This field is used in conjunction with the EPIBAUD register
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Byte Select Configuration
This bit enables byte select operation.
Value Description
0 No Byte Selects
Data is read and written as 16 bits.
1 Enable Byte Selects
Two EPI signals function as byte select signals to allow 8-bit
transfers. See Table 9-6 on page 466 for details on which EPI
signals are used.
January 23, 2012
493
Texas Instruments-Production Data