LM3S9D81 Datasheet, PDF (201/1277 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex

Stellaris^® LM3S9D81 Microcontroller
The Cortex-M3 processor core and the memory subsystem are not clocked in Deep-Sleep mode.
Peripherals are clocked that are enabled in the DCGCn registers when auto-clock gating is enabled
(see the RCC register) or the RCGCn registers when auto-clock gating is disabled. The system
clock source is specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used,
the internal oscillator source is powered up, if necessary, and other clocks are powered down. If
the PLL is running at the time of the WFI instruction, hardware powers the PLL down and overrides
the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting
in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep
mode before enabling the clocks that had been stopped during the Deep-Sleep duration. If the
PIOSC is used as the PLL reference clock source, it may continue to provide the clock during
Deep-Sleep. See page 226.
5.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a "raw" clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
5.4 Register Map
Table 5-8 on page 201 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register's address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 288.
Table 5-8. System Control Register Map
Offset Name
Type
Reset
0x000
0x004
DID0
DID1
RO
-
RO
-
Description
Device Identification 0
Device Identification 1
See
page
204
231
January 23, 2012
201
Texas Instruments-Production Data