ADC12D500RF Datasheet, PDF (49/74 Pages) Texas Instruments – ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC

17.3 FEATURES
The ADC12D800/500RF offers many features to make the
device convenient to use in a wide variety of applications.
Table 20 is a summary of the features available, as well as
details for the control mode chosen. "N/A" means "Not Appli-
cable."
TABLE 20. Features and Modes
Feature
Non-ECM
Control Pin
Active in ECM
ECM
Input Control and Adjust
AC/DC-coupled Mode
Selected via V_CMO
Yes
Selection
(Pin C2)
Not available
Input Full-scale Range
Adjust
Selected via FSR
(Pin Y3)
No
Selected via the Config Reg
(Addr: 3h and Bh)
Input Offset Adjust Setting Not available
N/A
Selected via the Config Reg
(Addr: 2h and Ah)
DES / Non-DES Mode
Selection
Selected via DES
(Pin V5)
No
Selected via the DES Bit
(Addr: 0h; Bit: 7)
DES Mode Input Selection
Not available
Selected via the DEQ, DIQ
N/A
Bits
(Addr: 0h; Bits: 6:5)
DESCLKIQ Mode
(Note 17)
Not available
N/A
Selected via the DCK Bit
(Addr: Eh; Bit: 6)
DES Timing Adjust
(Note 17)
Not available
Selected via the DES Timing
N/A
Adjust Reg
(Addr: 7h)
Sampling Clock Phase
Adjust
Not available
Selected via the Config Reg
N/A
(Addr: Ch and Dh)
Output Control and Adjust
DDR Clock Phase Selection
Selected via DDRPh
(Pin W4)
No
Selected via the DPS Bit
(Addr: 0h; Bit: 14)
DDR / SDR DCLK Selection Not available
N/A
Selected via the SDR Bit
(Addr: 0h; Bit: 2)
SDR Rising / Falling DCLK
Selection (Note 17)
Not available
Selected via the DPS Bit
N/A
(Addr: 0h; Bit: 14)
LVDS Differential Voltage
Amplitude Selection
Higher amplitude
only
N/A
Selected via the OVS Bit
(Addr: 0h; Bit: 13)
LVDS Common-Mode
Voltage Amplitude
Selected via V_BG
Yes
Selection (Note 17)
(Pin B1)
Not available
Output Formatting
Selection (Note 17)
Offset Binary only
N/A
Selected via the 2SC Bit
(Addr: 0h; Bit: 4)
Selected via TPM
Test Pattern Mode at Output
(Pin A4)
No
Selected via the TPM Bit
(Addr: 0h; Bit: 12)
Demux/Non-Demux Mode Selected via NDM
Selection
(Pin A5)
Yes
Not available
AutoSync
(Note 17)
Not available
N/A
Selected via the Config Reg
(Addr: Eh)
DCLK Reset
(Note 17)
Not available
N/A
Selected via the Config Reg
(Addr: Eh; Bit: 0)
Time Stamp
(Note 17)
Not available
N/A
Selected via the TSE Bit
(Addr: 0h; Bit: 3)
Calibration
On-command Calibration
Selected via CAL
(Pin D6)
Yes
Selected via the CAL Bit
(Addr: 0h; Bit: 15)
Power-on Calibration Delay Selected via CalDly
Selection
(Pin V4)
Yes
Not available
Default ECM State
N/A
Mid FSR value
Offset = 0 mV
Non-DES Mode
N/A
N/A
Mid skew offset
t_AD adjust disabled
0° Mode
DDR Mode
N/A
Higher amplitude
N/A
Offset Binary
TPM disabled
N/A
Master Mode,
RCOut1/2 disabled
DCLK Reset disabled
Time Stamp disabled
N/A
(CAL = 0)
N/A
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