ADC12D500RF Datasheet, PDF (10/74 Pages) Texas Instruments – ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC

Ball No.
Name
Y4/W5
RCLK+/-
Y5/U6
V6/V7
RCOut1+/-
RCOut2+/-
Equivalent Circuit
Description
Reference Clock Input. When the AutoSync
feature is active, and the ADC12D800/500RF is
in Slave Mode, the internal divided clocks are
synchronized with respect to this input clock. The
delay on this clock may be adjusted when
synchronizing multiple ADCs. This feature is
available in ECM via Control Register (Addr: Eh).
(Note 18)
Reference Clock Output 1 and 2. These signals
provide a reference clock at a rate of CLK/4,
when enabled, independently of whether the
ADC is in Master or Slave Mode. They are used
to drive the RCLK of another
ADC12D800/500RF, to enable automatic
synchronization for multiple ADCs (AutoSync
feature). The impedance of each trace from
RCOut1 and RCOut2 to the RCLK of another
ADC12D800/500RF should be 100Ω differential.
Having two clock outputs allows the auto-
synchronization to propagate as a binary tree.
Use the DOC Bit (Addr: Eh, Bit 1) to enable/
disable this feature; default is disabled.
(Note 18)
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