ADC08D1520QML-SP_17 Datasheet, PDF (49/58 Pages) Texas Instruments – Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

ADC08D1520QML-SP
www.ti.com
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
To use this feature in the Non-Extended Control Mode, tie pin 127 to V_A/2 and the signal at the I- channel input
will be sampled by both converters.
In the Extended Control Mode, either input may be used for dual edge sampling. See Dual-Edge Sampling.
Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1520 to be entirely powered down (PD) or the Q-
Channel channel to be powered down and the I- Channel to remain active. See Power Down for details on the
power down feature.
The digital data (+/-) output pins are put into a high impedance state when the PD pin for the respective channel
is high. Upon return to normal operation, the pipeline will contain meaningless information and must be flushed.
If the PD input is brought high while a calibration is running, the device will not go into power down until the
calibration sequence is complete. However, if power is applied and PD is simultaneously ramped, the device will
not calibrate until the PD input goes low. When PD is high and a calibration is initiated, the request for calibration
is completely ignored. Refer to Power Down
THE DIGITAL OUTPUTS
The ADC08D1520 demultiplexes the output data of each of the two ADCs on the die onto two LVDS output
buses (total of four buses, two for each ADC). For each of the two converters, the results of successive
conversions started on the odd falling edges of the CLK+ pin are available on one of the two LVDS buses, while
the results of conversions started on the even falling edges of the CLK+ pin are available on the other LVDS bus.
This means that, the word rate at each LVDS bus is 1/2 the ADC08D1520 input clock rate and the two buses
must be multiplexed to obtain the entire 1.5 GSPS conversion result.
Since the minimum recommended input clock rate for this device is 200 MSPS (Non DES Mode), the effective
rate can be reduced to as low as 100 MSPS by using the results available on just one of the two LVDS buses
and a 200 MHz input clock, decimating the 200 MSPS data by two.
There is one LVDS output clock pair (DCLK+/-) available for use to latch the LVDS outputs on all buses. Whether
the data is sent at the rising or falling edge of DCLK is determined by the sense of the OutEdge pin, as described
in Output Edge Synchronization.
DDR (Double Data Rate) clocking can also be used. In this mode a word of data is presented with each edge of
DCLK, reducing the DCLK frequency to 1/4 the input clock frequency. See the Timing Diagrams section for
details.
The OutV pin is used to set the LVDS differential output levels. See LVDS Output Level Control.
The output format is Offset Binary. Accordingly, a full-scale input level with V_IN+ positive with respect to V_IN− will
produce an output code of all ones, a full-scale input level with V_IN− positive with respect to V_IN+ will produce an
output code of all zeros and when V_IN+ and V_IN− are equal, the output code will vary between codes 127 and
128.
POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
33 µF capacitor should be placed within an inch (2.5 cm) of the A/D converter power pins. A 0.1 µF capacitor
should be placed as close as possible to each V_A pin, preferably within one-half centimeter. Leadless chip
capacitors are preferred because they have low lead inductance.
The V_A and V_DR supply pins should be isolated from each other to prevent any digital noise from being coupled
into the analog portions of the ADC. A ferrite choke, such as the JW Miller FB20009-3B, is recommended
between these supply lines when a common source is used for them.
As is the case with all high speed converters, the ADC08D1520 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in a system where a lot of digital power is being
consumed should not be used to supply power to the ADC08D1520. The ADC supplies should be the same
supply used for other analog circuitry, if not a dedicated supply.
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