ADC08D1520QML-SP_17 Datasheet, PDF (29/58 Pages) Texas Instruments – Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

ADC08D1520QML-SP
www.ti.com
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The ADC08D1520 is a versatile A/D Converter with an innovative architecture permitting very high speed
operation. The controls available ease the application of the device to circuit solutions. Optimum performance
requires adherence to the provisions discussed here and in the Applications Information Section.
While it is not recommended in radiation environments to allow an active pin to float, pins 4, 14, 52 and 127 of
the ADC08D1520 are designed to be left floating without jeopardy in non radiation environments. In all
discussions throughout this data sheet, whenever a function is called by allowing a control pin to float, connecting
that pin to a potential of one half the V_A supply voltage is recommended for radiation environments.
OVERVIEW
The ADC08D1520 uses a calibrated folding and interpolating architecture that achieves over 7.25 effective bits.
The use of folding amplifiers greatly reduces the number of comparators and power consumption. Interpolation
reduces the number of front-end amplifiers required, minimizing the load on the input signal and further reducing
power requirements. In addition to other things, on-chip calibration reduces the INL bow often seen with folding
architectures. The result is an extremely fast, high performance, low power converter.
The analog input signal that is within the converter's input voltage range is digitized to eight bits at speeds of 200
MSPS to 1.7 GSPS, typical. Differential input voltages below negative full-scale will cause the output word to
consist of all zeroes. Differential input voltages above positive full-scale will cause the output word to consist of
all ones. Either of these conditions at either the I- or Q- Channel input will cause the OR (Out of Range) output to
be activated. This single OR output indicates when the output code from one or both of the channels is below
negative full scale or above positive full scale.
Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed
Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-
Demultiplexed Mode is selected, that output data rate on channels DI and DQ are at the same rate as the input
sample clock.
The output levels may be selected to be normal or reduced. Using reduced levels saves power but could result in
erroneous data capture of some or all of the bits, especially at higher sample rates and in marginally designed
systems.
Calibration
The ADC08D1520 has a calibration feature which must be invoked by the user. If the device is powered-up in the
Extended Control Mode, the registers will be in an unknown state and no calibration is performed. For the initial
calibration after power-up, we recommend that the registers first be programmed to a known state before
performing a calibration or the part be calibrated in the pin control mode. All subsequent calibrations can be run
in either the Non-Extended Control Mode or the Extended Control Mode.
The calibration algorithm consists of two portions. The first portion is calibrating the analog input. This calibration
trims the 100 Ω analog input differential termination resistor and minimizes full-scale error, offset error, DNL and
INL, resulting in maximizing SNR, THD, SINAD (SNDR) and ENOB. This portion of the calibration can be
disabled by programming the Resistor Trim Disable (RTD) bit in the Extended Configuration register in the
Extended Control Mode. Disabling the input termination resistor is not recommended for the initial calibration
after power-up. The second portion of the calibration cycle is the ADC calibration in which internal bias currents
are set. The ADC calibration is performed regardless of the RTD bit setting. Running the calibration is an
important part of this chip’s functionality and is required in order to obtain specified performance. In addition to
the requirement that a calibration be run at power-up, a calibration must be run whenever the FSR pin is
changed. For best performance, we recommend that a calibration be run after application of power once the
power supplies have settled and the part temperature has stabilized. Further calibrations should be run whenever
the operating temperature changes significantly relative to the specific system performance requirements. See
Initiating Calibration for more information. Calibration can not be initiated or run while the device is in the Power-
Down Mode. SeePower Down for information on the interaction between Power down and calibration.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC08D1520QML-SP
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