UCC28950_15 Datasheet, PDF (48/74 Pages) Texas Instruments – UCC28950 Green Phase-Shifted Full-Bridge Controller With Synchronous Rectification

UCC28950
SLUSA16C – MARCH 2010 – REVISED NOVEMBER 2015
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8.2.2.9 Input Capacitance (C_IN)
The input voltage in this design is 390 V_DC, which is generally fed by the output of a PFC boost pre-regulator.
The input capacitance is generally selected based on holdup and ripple requirements.
NOTE
The delay time needed to achieve ZVS can act as a duty cycle clamp (D_CLAMP).
Calculate tank frequency:
f_R = _2p
1
L_S ´ (2 ´ C_{OSS _ QA _ AVG} )
(97)
Estimated delay time:
2
t
DELAY
=
f _R´4
»
314 ns
(98)
Effective duty cycle clamp (D_CLAMP):
D_CLAMP
§1
¨
©
2
u
f_SW
·
t_DELAY
¸
¹
u
2
u
f_SW
94%
(99)
V_DROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input
voltage would only drop down this low during a brownout or line-drop condition if this converter was following a
PFC pre-regulator.
V_DROP
=
æ
ç
è
2 ´ D_CLAMP
´ V_RDSON + a1´ (V_OUT
D_CLAMP
+
V_RDSON
)
ö
÷
ø
=
276.2 V
(100)
C_IN was calculated based on one line cycle of holdup:
1
2
´
P
OUT
´
60
Hz
( ) C
IN
³
V2
IN
-
V2
DROP
» 364 mF
(101)
Calculate high frequency input capacitor RMS current (I_CINRMS).
I
=
CINRMS
I²
PRMS1
-
æ
ç
è
P
OUT
V´
INMIN
ö²
÷
a1_ø
= 1.8 A
(102)
To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen
from Panasonic part number EETHC2W331EA.
C
IN
=
330 mF
(103)
This capacitor has a high frequency (ESR_CIN) of 150 mΩ, measured with an impedance analyzer at 200 kHz.
ESR
CIN
=
0.150 W
(104)
Estimate C_IN power dissipation (P_CIN):
P
CIN
=
I
2
CINRMS
´
ESR
CIN
=
0.5 W
(105)
Recalculate remaining power budget:
P
BUDGET
=
P
BUDGET
-
P
CIN
»
6.0 W
(106)
There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control
device and all resistors supporting the control device.
48
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