UCC28950_15 Datasheet, PDF (30/74 Pages) Texas Instruments – UCC28950 Green Phase-Shifted Full-Bridge Controller With Synchronous Rectification

UCC28950
SLUSA16C – MARCH 2010 – REVISED NOVEMBER 2015
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Feature Description (continued)
7.3.15 Synchronization (SYNC)
The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all
SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as
master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency
equal to 2X the converter frequency F_SW(nom) and 0.5 duty cycle. The controller configured as a slave (resistor
between RT and GND and 825-kΩ resistor between SS_EN pin to GND) does not generate the synchronization
pulses. The Slave controller synchronizes its own clock to the falling edge of the synchronization signal thus
operating 90° phase shifted versus the master converter’s frequency F_SW(nom).
The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the
transformer. In the case of the UCC28950 this means that the output inductor operates at 2 x F_SW(nom). This
means that the 90° phase shift between master and slave controllers gives a 180° phase shift between the
currents in the output inductors and hence maximum ripple cancellation. For more information about
synchronizing more than two UCC28950 devices, see Synchronizing Three or More UCC28950 Phase-Shifted,
Full-Bridge Controllers, SLUA609.
If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to
GND via a 10-kΩ resistor will reduce noise pickup and switching frequency jitter.
• If any converter is configured as a slave, the SYNC frequency must be greater than or equal to 1.8 times the
converter frequency.
• Slave converter does not start until at least one synchronization pulse has been received.
• If any or all converters are configured as slaves, then each converter operates at its own frequency without
synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of
synchronization pulses at the slave converter, then the controller uses its own internal clock pulses to
maintain operation based on the R_T value that is connected to GND in the slave converter.
• In master mode, SYNC pulses start after SS pin passes its enable threshold which is 0.55 V.
• Slave starts generating SS/EN voltage even though synchronization pulses have not been received.
• It is recommended that the SS on the master controller starts before the SS on the slave controller; therefore
SS/EN pin on master converter must reach its enable threshold voltage before SS/EN on the slave converter
starts for proper operation. On the same note, it’s recommended that T_MIN resistors on both master and slave
are set at the same value.
CLK
SYNC_OUT
A
B
Figure 43. SYNC_OUT (Master Mode) Timing Diagram
SYNC_IN
CLK
A
B
Figure 44. SYNC_IN (Slave Mode) Timing Diagram
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