ADS5560 Datasheet, PDF (48/61 Pages) Texas Instruments – 16-BIT, 40/80 MSPS ADCs WITH DDR LVDS/CMOS OUTPUTS

ADS5560, ADS5562
SLWS207B – MAY 2008 – REVISED JANUARY 2016
www.ti.com
Typical Application (continued)
The SNR of the amplifier and filter can be calculated from the noise specifications in the data sheet for the
amplifier, the amplitude of the signal and the bandwidth of the filter. The noise from the amplifier is band-limited
by the filter, and the rolloff of the filter depends on the order of the filter. Therefore, replacing the filter rolloff with
an equivalent brick-wall filter bandwidth is convenient. For example, a 1st order filter can be approximated by a
brick-wall filter with bandwidth of 1.57 times the bandwidth of the 1st order filter. For this design, assume a 1st
order filter is used. Use Equation 7 to calculate the amplifier and filter noise.
SNR_Amp+Filter
=
10
´
log
æ
ççè
V_O2
E^2FILTEROUT
ö
÷÷ø
=
20
´
æ
log_ç
è
V_O
E_FILTEROUT
ö
÷
ø
Where
• V_O = the amplifier output signal (which will be full scale input of the ADC expressed in rms)
• E_FILTEROUT = E_NAMPOUT × √ENB
– E_NAMPOUT = the output noise density of the LMH6552 (1.1 nV/√Hz times amplifier gain)
– ENB = the brick-wall equivalent noise bandwidth of the filter
(7)
In Equation 7, the parameters of the equation may be seen to be in terms of signal amplitude in the numerator
and amplifier noise in the denominator, or SNR. For the numerator, use the full-scale voltage specification of the
ADS5562 device, or 3.56-V peak-to-peak differential. Because Equation 7 requires the signal voltage to be in
rms, convert 3.56 V_PP to 1.26 V rms.
The noise specification for the LMH6552 device is listed as 1.1 nV/√Hz times the amplifier gain. Therefore, use
this value to integrate the noise component from DC out to the filter cutoff, using the equivalent brick wall filter of
40 MHz × 1.57, or 62.8 MHz. The result of 1.1 nV/√Hz over √62.8 MHz times gain yields 8717 nV, or 8.717 µV,
assuming a gain factor of 2 for the amplifier.
Using 1.26-V rms for V_O and 8.717 µV for E_FILTEROUT, the SNR of the amplifier and filter as given by Equation 7 is
approximately 103.2 dB.
Taking the SNR of the ADC as 83 dB from Figure 61, and SNR of the amplifier and filter as 103.2 dB, Equation 6
predicts the system SNR to be 82.96 dB. In other words, the SNR of the ADC and the SNR of the front end
combine as the square root of the sum of squares, and because the SNR of the amplifier front end is much
greater than the SNR of the ADC in this example, the SNR of the ADC dominates Equation 6 and the system
SNR is almost the SNR of the ADC. The assumed design requirement is 82 dB, and after a clocking solution was
selected and an amplifier or filter solution was selected, the predicted SNR of is 82.96 dB. At this point, consider
making tradeoffs of either the clocking specification or amplifier gain to see how such tradeoffs begin to affect the
expected system performance.
48
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