TMS470MF06607 Datasheet, PDF (47/64 Pages) Texas Instruments – TMS470MF06607 16/32-Bit RISC Flash Microcontroller

TMS470MF06607
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SPNS157C – JANUARY 2012
5.3 SPIn Master Mode Timing Parameters
Table 5-16. SPIn Master Mode External Timing Parameters (CLOCK PHASE = 0, SPInCLK = output,
SPInSIMO = output, and SPInSOMI = input)^(1)(2)(3)
(see Figure 5-13 and Figure 5-14)
NO.
1
2 ⁽⁵⁾
t_c(SPC)M
t_w(SPCH)M
t_w(SPCL)M
Cycle time, SPICLK⁽⁴⁾
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low (clock polarity =
1)
MIN
90
0.5t_c(SPC)M - t_r
0.5t_c(SPC)M - t_f
MAX
256t_c(VCLK)
0.5t_c(SPC)M + 5
UNIT
0.5t_c(SPC)M + 5
t_w(SPCL)M
3 ⁽⁵⁾
t_w(SPCH)M
Pulse duration, SPICLK low (clock polarity =
0)
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t_c(SPC)M - t_f
0.5t_c(SPC)M - t_r
0.5t_c(SPC)M + 5
0.5t_c(SPC)M + 5
4 ⁽⁵⁾
t_{d(SIMO-SPCL)M}
t_{d(SIMO-SPCH)M}
Delay time, SPISIMO data valid before
SPICLK low (clock polarity = 0)
Delay time, SPISIMO data valid before
SPICLK high (clock polarity = 1)
0.5t_c(SPC)M - 15
0.5t_c(SPC)M - 15
5 ⁽⁵⁾
t_{v(SPCL-SIMO)M}
t_{v(SPCH-SIMO)M}
Valid time, SPISIMO data valid
(clock polarity = 0)
Valid time, SPISIMO data valid
(clock polarity = 1)
0.5t_c(SPC)M - t_f(SPC)
0.5t_c(SPC)M - t_r(SPC)
6 ⁽⁵⁾
t_{su(SOMI-SPCL)M}
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
4
ns
t_{su(SOMI-SPCH)M}
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
4
7 ⁽⁵⁾
t_{h(SPCL-SOMI)M}
Hold time, SPISOMI data valid after SPICLK
low (clock polarity = 0)
8
t_{h(SPCH-SOMI)M}
Hold time, SPISOMI data valid after SPICLK
high (clock polarity = 1)
8
8 ^{(5) (6)} t_C2TDELAY
9 ^{(5) (6)}
t_T2CDELAY
10⁽⁶⁾ _tSPIENA
Setup time CS active until SPICLK high
(clock polarity = 0)
Setup time CS active until SPICLK low
(clock polarity = 1)
Hold time SPICLK low until CS inactive
(clock polarity = 0)
Hold time SPICLK high until CS inactive
(clock polarity = 1)
SPIENAn sample point
(C2TDELAY+CSHOLD+2)* (C2TDELAY+CSHOLD+
t_c(VCLK) - t_f(SPICS) +
t_r(SPICLK)-6
2)*t_c(VCLK) - t_f(SPICS) +
t_r(SPICLK)+38
(C2TDELAY+CSHOLD+2)* (C2TDELAY+CSHOLD+
t_c(VCLK) - t_f(SPICS) +
t_f(SPICLK)-6
2)*t_c(VCLK) - t_f(SPICS) +
t_f(SPICLK)+38
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_f(SPICLK) +
t_r(SPICS)-28
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_f(SPICLK) +
t_r(SPICS)+8
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_r(SPICLK) +
t_r(SPICS)-28
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) +
t_c(VCLK) - t_r(SPICLK) +
t_r(SPICS)+8
C2TDELAY * t_c(VCLK) -
t_f(SPICS)
C2TDELAY *t_c(VCLK)
ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is clear.
(2) t_c(VCLK) = interface clock cycle time = 1 / f_(VCLK).
(3) For rise and fall timings, see Table 5-13.
(4) When the SPI is in Master mode, the following must be true:
• For PS values from 1 to 255: t ≥ (PS +1)t_c(VCLK) ≥ 90 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
• For PS values of 0: t_c(SPC)M = 2t_c(VCLK) ≥ 90 ns.
(5) The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY are programmed in the SPIDELAY register.
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
47
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