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THS4541-Q1 Datasheet, PDF (47/60 Pages) Texas Instruments – 850-MHz Fully Differential Amplifier
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Typical Applications (continued)
10.2.2 Interfacing to High-Performance ADCs
Vcc
50-
Source
D1
BAV99
R4
R7
59
205
R6
205
R9
499
C1 Vcc
0.2 F
Vocm
±
+
FDA
±
+
PD
Vcc
R1
49.9
2-to-3 for
ac-coupled Vin
2
31
JP1
C7
1F
R5
59
2-to-1 for
dc-coupled Vin
R8
499
THS4541-Q1
SLOS930A – NOVEMBER 2015 – REVISED NOVEMBER 2015
R12
35.7
R13
35.7
L2
250 nH
R16
6.2
C5
33 pF
L3
250 nH
C6
180 pF
R15
442
R17
6.2
ADC
Input
ADC
Input
0.95 V
ADC Vcm
Vcc R11 Output
100
C3
10 nF
Figure 80. DC-Coupled, Bipolar Input Gain of 2 V/V Single-Ended to Differential Interface to ADC
10.2.2.1 Design Requirements
In this example design, an impedance matched input assuming a 50-Ω source is implemented with a DC-coupled
gain of 2 V/V to the ADC. This configuration effectively reduces the required full-scale input to ±0.5 V for a 2-VPP
full-scale input ADC. Add a low insertion-loss interstage filter to the ADC to control the broadband noise where
the goal is to show minimal SNR reduction in the FFT, as well as minimal degradation in SFDR performance.
10.2.2.2 Detailed Design Procedure
The THS4541-Q1 provides a very flexible element for interfacing from a variety of sources to a wide range of
ADCs. Because all precision and high-speed ADCs require a differential input on a common-mode voltage, this
design is the primary application for the THS4541-Q1.
The THS4541-Q1 provides a simple interface to a wide variety of precision SAR, ΔΣ, or higher-speed pipeline
ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than typically
required in the signal path to the ADC inputs is provided by the THS4541-Q1. For instance, the gain of 2 single-
ended to differential design example provides approximately a 500-MHz, small-signal bandwidth. Even if the
source signal is Nyquist bandlimited, this broad bandwidth can possibly integrate enough THS4541-Q1 noise to
degrade the SNR through the ADC if the broadband noise is not bandlimited between the amplifier and ADC.
Figure 80 shows an example DC-coupled, gain of 2 interface with a controlled, interstage-bandwidth filter
implemented on the demonstration board for the JESD digital-output interface, ADC34J22 (a 50-MSPS, quad,
12-bit ADC). This board is called the DEV-ADC34J22 ADC HSMC MODULE with complete documentation at
http://dallaslogic.com/prod_dev-adc34j/.
Designed for a DC-coupled 50Ω input match, this design starts with a 499-Ω feedback resistor, and provides a
gain of 2.35V/V to the THS4541-Q1 output pins. The third-order interstage, low-pass filter provides a 20-MHz
Bessel response with a 0.85 V/V insertion loss to the ADC, providing a net gain of 2 V/V from board edge to the
ADC inputs. Although the THS4541-Q1 can absorb overdrives, an external protection element is added using the
BAV99 low-capacitance device, shown in Figure 80. For DC-coupled testing, pins 1 and 2 are jumpered together.
When the source is an AC-coupled, 50-Ω source, pins 2 and 3 are jumpered to maintain differential balance. FFT
testing normally uses a bandpass filter into the board; an AC-coupled source. A typical 5-MHz, full-scale, single-
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