ADC3241 Datasheet, PDF (47/82 Pages) Texas Instruments – Analog-to-Digital Converters

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9 Detailed Description
ADC3241, ADC3242, ADC3243, ADC3244
SBAS671C – JULY 2014 – REVISED MARCH 2016
9.1 Overview
The ADC324x are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-
digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency
signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock
architecture design while the SYSREF input enables complete system synchronization. The ADC324x family
supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high system
integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over
two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the
bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as LVDS outputs.
9.2 Functional Block Diagram
INAP
INAM
CLKP
CLKM
SYSREFP
SYSREFM
INBP
INBM
VCM
14-Bit
ADC
Digital Encoder
and Serializer
Divide by
1,2,4
Bit Clock
PLL
Frame Clock
Common
Mode
14-Bit
ADC
Digital Encoder
and Serializer
Configuration Registers
DA0P
DA0M
DA1P
DA1M
DCLKP
DCLKM
FCLKP
FCLKM
DB0P
DB0M
DB1P
DB1M
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