ADC3241 Datasheet, PDF (41/82 Pages) Texas Instruments – Analog-to-Digital Converters

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ADC3241, ADC3242, ADC3243, ADC3244
SBAS671C – JULY 2014 – REVISED MARCH 2016
Typical Characteristics: ADC3244 (continued)
Typical values are at T_A = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-V_PP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from f_S / 2 when chopper is enabled, unless otherwise noted.
92
DVDD = 1.7 V
DVDD = 1.85 V
DVDD = 1.75 V
DVDD = 1.9 V
90
DVDD = 1.8 V
73
DVDD = 1.7 V
DVDD = 1.85 V
DVDD = 1.75 V
DVDD = 1.9 V
72.6
DVDD = 1.8 V
88
72.2
86
71.8
84
71.4
82
-40
-15
10
35
60
Temperature (°C)
85
D125
71
-40
-15
10
35
60
Temperature (°C)
85
D126
Figure 118. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
74.5
94
SNR
SFDR
74
93
73.5
92
73
91
72.5
90
72
89
71.5
88
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
Differential Clock Amplitude (Vpp)
D127
Figure 119. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
77
95
SNR
SFDR
75
90
73
85
71
80
69
75
67
70
65
65
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
Differential Clock Amplitude (Vpp)
D128
Figure 120. Performance vs Clock Amplitude (40 MHz)
74.2
95
SNR
SFDR
73.8
94
73.4
93
73
92
72.6
91
Figure 121. Performance vs Clock Amplitude (150 MHz)
72.4
90
SNR
SFDR
72.2
87.5
72
85
71.8
82.5
71.6
80
72.2
90
30 35 40 45 50 55 60 65 70
Input Clock Duty Cycle (%)
D129
71.4
77.5
30 35 40 45 50 55 60 65 70
Input Clock Duty Cycle (%)
D130
Figure 122. Performance vs Clock Duty Cycle (30 MHz)
Figure 123. Performance vs Clock Duty Cycle (150 MHz)
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41
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