ADC07D1520 Datasheet, PDF(47/53 Page) Texas Instruments – Low Power, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

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ADC07D1520 Datasheet, PDF (47/53 Pages) Texas Instruments – Low Power, 7-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter

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ADC07D1520

TABLE 10. Non-Extended Control Mode Operation

(Pin 41 Floating and Pin 52 Floating or Logic High)

Low

High

Floating

Reduced VOD

Normal VOD

4 OutEdge = Neg OutEdge = Pos

N/A

DDR

127 CalDly Short

CalDly Long

DES

Reduced VIN

Normal VIN

Extended Control Mode

Pin 3 can be either logic high or low in the Non-extended Control Mode. Pin 14 must not be left floating to select this mode. See

1.2 NON-EXTENDED AND EXTENDED CONTROL MODE for more information.

Pin 4 can be logic high, logic low or left floating in the Non-extended Control Mode. In the Non-extended Control Mode, pin 4 logic

high or low defines the edge at which the output data transitions. See 2.4.3 Output Edge Synchronization for more information. If

this pin is floating, the output Data Clock (DCLK) is a Double Data Rate (DDR) clock (see 1.1.5.3 Double Data Rate and Single

Data Rate) and the output edge synchronization is irrelevant since data is clocked out on both DCLK edges.

Pin 127, if it is logic high or low in the Non-extended Control Mode, sets the calibration delay. If pin 127 is floating, the calibration

delay is short and the converter performs in DES Mode.

TABLE 11. Extended Control Mode Operation

(Pin 41 Logic Low or Pin 14 Floating and Pin 52 Floating or Logic High)

Function

SCLK (Serial Clock)

SDATA (Serial Data)

127

SCS (Serial Interface Chip Select)

2.10 COMMON APPLICATION PITFALLS

Failure to write all register locations when using extended control mode. When using the serial interface, all nine address

locations must be written at least once with the default or desired values before calibration and subsequent use of the ADC.

Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, no input should go more than 150

mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a transient basis may not only cause

faulty or erratic operation, but may impair device reliability. It is not uncommon for high speed digital circuits to exhibit undershoot

that goes more than a volt below ground. Controlling the impedance of high speed lines and terminating these lines in their char-

acteristic impedance should control overshoot.

Care should be taken not to overdrive the inputs of the ADC07D1520. Such practice may lead to conversion inaccuracies and even

to device damage.

Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in 1.1.4 The Analog Inputs and 2.2 THE

ANALOG INPUT, the Input common mode voltage must remain within 50 mV of the VCMO output , which varies with temperature

and must also be tracked. Distortion performance will be degraded if the input common mode voltage is more than 50 mV from

VCMO .

Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier to drive the

ADC07D1520 as many high speed amplifiers will have higher distortion than the ADC07D1520, resulting in overall system perfor-

mance degradation.

Driving the VBG pin to change the reference voltage. As mentioned in 2.1 THE REFERENCE VOLTAGE, the reference voltage

is intended to be fixed by FSR pin or Full-Scale Voltage Adjust register settings. Over driving this pin will not change the full scale

value, but can be used to change the LVDS common mode voltage from 0.8V to 1.2V by tying the VBG pin to VA.

Driving the clock input with an excessively high level signal. The ADC input clock level should not exceed the level described

in the Operating Ratings Table or the input offset could change.

Inadequate input clock levels. As described in 2.3 THE CLOCK INPUTS, insufficient input clock levels can result in poor perfor-

mance. Excessive input clock levels could result in the introduction of an input offset.

Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having other signals

coupled to the input clock signal trace. This will cause the sampling interval to vary, causing excessive output noise and a

reduction in SNR performance.

Failure to provide adequate heat removal. As described in 2.6.2 Thermal Management, it is important to provide adequate heat

removal to ensure device reliability. This can be done either with adequate air flow or the use of a simple heat sink built into the

board. The backside pad should be grounded for best performance.

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