LM3S1627_16 Datasheet, PDF (468/727 Pages) Texas Instruments – Stellaris Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Table 12-1. UART Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
U1Tx
42
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has
IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
12.3
Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 487). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
12.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 12-2 on page 468 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 12-2. UART Character Frame
UnTX
1
0
n
Start
LSB
MSB
5-8 data bits
1-2
stop bits
Parity bit
if enabled
12.3.2
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 483) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor
(UARTFBRD) register (see page 484). The baud-rate divisor (BRD) has the following relationship
to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part,
separated by a decimal place.)
BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate)
where UARTSysClk is the system clock connected to the UART.
468
July 17, 2014
Texas Instruments-Production Data