TPS650860_16 Datasheet, PDF (46/94 Pages) Texas Instruments – Configurable Multirail PMU for Multicore Processors

TPS650860
SWCS128A – MARCH 2015 – REVISED DECEMBER 2015
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5.9.13 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP-Programmable]
Figure 5-30. BUCK5CTRL Register
Bit
7
6
5
4
3
2
Bit Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
TPS650860
0
0
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
BUCK5_
MODE
0
R/W
0
BUCK5_DIS
1
R/W
Bit Field
5:2 RESERVED
1
BUCK5_MODE
0
BUCK5_DIS
Table 5-18. BUCK5CTRL Register Descriptions
Type Reset
R/W 1111
R/W OTP-Programmable
R/W OTP-Programmable
Description
Reserved bits: Do not write to 0. These bits must stay 1 for sleep
control reasons.
This field sets the BUCK5 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
BUCK5 Disable Bit. Writing 0 to this bit forces BUCK5 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
5.9.14 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = OTP-Programmable]
Figure 5-31. BUCK6CTRL Register
Bit
7
6
5
4
3
2
Bit Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
TPS650860
0
0
1
1
1
1
Access
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1
BUCK6_
MODE
0
R/W
0
BUCK6_DIS
1
R/W
Bit Field
5:2 RESERVED
1
BUCK6_MODE
0
BUCK6_DIS
Table 5-19. BUCK6CTRL Register Descriptions
Type Reset
R/W 1111
R/W OTP-Programmable
R/W OTP-Programmable
Description
Reserved bits: Do not write to 0. These bits must stay 1 for sleep
control reasons.
This field sets the BUCK6 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
BUCK6 Disable Bit. Writing 0 to this bit forces BUCK6 to turn off
regardless of any control input pin (CTL1–CTL6) status.
0: Disable.
1: Enable.
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Detailed Description
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