TMS320C5545 Datasheet, PDF (46/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C5545
SPRS853C – JULY 2013 – REVISED MARCH 2016
www.ti.com
5.6.5 Power Supplies
The device includes four core voltage-level supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3), and
four I/O supplies (DV_DDIO, DV_DDRTC , USB_V_DDOSC, and USB_V_DDA3P3), as well as four analog supplies
(LDOI, V_{DDA_PLL}, V_{DDA_ANA}, and USB_V_DDPLL). Some TI power-supply devices include features that
facilitate power sequencing—for example, Auto-Track and Slow-Start and Enable features. For more
information regarding TI's power management products and suggested devices to power TI DSPs, see
www.ti.com/processorpower.
5.6.5.1 Power-Supply Sequencing
NOTE
The external reset signal on the RESET pin must be held low until all of the external power
supplies reach their operating voltage conditions.
The device includes four core voltage-level supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3), and
four I/O supplies (DV_DDIO, DV_DDRTC, USB_V_DDOSC, and USB_V_DDA3P3).
If the DSP_LDO is disabled (DSP_LDO_EN = high) and an external regulator supplies power to the CPU
Core (CV_DD), the external reset signal (RESET) must be held asserted until all of the supply voltages
reach their valid operating ranges.
The I/O design allows either the core supplies (CV_DD, CV_DDRTC , USB_V_DD1P3, USB_V_DDA1P3 ) or the I/O
supplies (DV_DDIO, DV_DDRTC , USB_V_DDOSC, and USB_V_DDA3P3 ) to be powered up for an indefinite period of
time while the other supply is not powered if the following constraints are met:
1. All maximum ratings and recommended operating conditions are satisfied.
2. All warnings about exposure to maximum rated and recommended conditions, particularly junction
temperature are satisfied. These apply to power transitions as well as normal operation.
3. Bus contention while core supplies are powered must be limited to 100 hours over the projected
lifetime of the device.
4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings.
If the USB subsystem is used, the subsystem must be powered up in the following sequence:
1. USB_V_DDA1P3 and USB_V_DD1P3
2. USB_V_DDA3P3
3. USB_V_BUS
If the USB subsystem is unused, the following can be powered off:
• USB Core
– USB_V_DD1P3
– USB_V_DDA1P3
• USB PHY and I/O level supplies
– USB_V_DDOSC
– USB_V_DDA3P3
– USB_V_DDPLL
A supply bus is powered up when the voltage is within the TI-recommended operating range. The supply
bus is powered down when the voltage is below that range, either stable or while in transition.
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Specifications
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