TMS320C5545 Datasheet, PDF (1/128 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C5545
SPRS853C – JULY 2013 – REVISED MARCH 2016
TMS320C5545 Fixed-Point Digital Signal Processor
1 Device Overview
1.1 Features
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• Core:
– High-Performance, Low-Power, TMS320C55x
Fixed-Point Digital Signal Processor
• 16.67-, 10-ns Instruction Cycle Time
• 60-, 100-MHz Clock Rate
• One or Two Instructions Executed per Cycle
• Dual Multiply-and-Accumulate (MAC) Units
(up to 200 Million Multiply-Accumulates per
Second [MMACS])
• Two Arithmetic and Logic Units (ALUs)
• Three Internal Data and Operand Read
Buses and Two Internal Data and Operand
Write Buses
• Software-Compatible With C55x Devices
– 320KB of Zero-Wait State On-Chip RAM,
Composed of:
• 64KB of Dual-Access RAM (DARAM),
8 Blocks of 4K × 16-Bit
• 256KB of Single-Access RAM (SARAM),
32 Blocks of 4K × 16-Bit
– 128KB of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
– Tightly Coupled Fast Fourier transform (FFT)
Hardware Accelerator
• Peripheral:
– Direct Memory Access (DMA) Controller
• Four DMA With 4 Channels Each (16
Channels Total)
– Three 32-Bit General-Purpose (GP) Timers
• One Selectable as a Watchdog or GP
– Two Embedded Multimedia Card (eMMC) or
Secure Digital (SD) Interfaces
– Universal Asynchronous Receiver/Transmitter
(UART)
– Serial Port Interface (SPI) With Three Chip
Selects
– Master and Slave Inter-Integrated Circuit (I²C
Bus)
– Four Inter-IC Sound (I2S Bus) for Data
Transport
– Device USB Port With Integrated 2.0 High-
Speed PHY That Supports:
• USB 2.0 Full- and High-Speed Device
– LCD Bridge With Asynchronous Interface
– 10-Bit 3-Input Successive Approximation (SAR)
Analog-to-Digital Converter (ADC)
– IEEE 1149.1 (JTAG)
Boundary-Scan-Compatible
– 32 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• Configure up to 20 GPIO Pins at the Same
Time
• Power:
– Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
– Three I/O Isolated Power Supply Domains: RTC
I/O, USB PHY, and DV_DDIO
– Three integrated LDOs (DSP_LDO, ANA_LDO,
and USB_LDO) to Power the Isolated Domains:
DSP Core, Analog, and USB Core, Respectively
– 1.05-V Core (60 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
– 1.3-V Core (100 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
• Clock:
– External Clock Source Through CLKIN Pin That
Supports 11.2896-, 12.000-, and 12.288-MHz
Clock Frequencies
– Real-Time Clock (RTC) With 32.768-kHz Crystal
Input, Separate Clock Domain, and Separate
Power Supply
– Low-Power, Software-Programmable Phase-
Locked Loop (PLL) Clock Generator
• Bootloader:
– On-Chip ROM Bootloader (RBL) to Boot From
SPI EEPROM, SPI Serial Flash or I²C EEPROM
eMMC, SD, SDHC, UART, and USB
• Package:
– 118-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZQW Suffix)
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.