DP8390D Datasheet, PDF (46/58 Pages) National Semiconductor (TI) – NIC Network Interface Controller

15 0 Switching Characteristics (Continued)
DMA Memory Read
TL F 8582 – 82
te ^Symbol
Parameter
Min
Max
Units
bcrl
Bus Clock to Read Strobe Low
43
ns
bcrh
Bus Clock to Read Strobe High
40
ns
ds
Data Setup to Read Strobe High
25
ns
dh
Data Hold from Read Strobe High
0
ns
le ^drw
DMA Read Strobe Width Out
2 bcyc b 15
ns
raz
Memory Read High to Address TRI-STATE
(Notes 1 2)
bch a 40
ns
asds
Address Strobe to Data Strobe
bcl a 10
ns
dsada
Data Strobe to Address Active
bcyc b 10
ns
o _avrh
Address Valid to Read Strobe High
3 bcyc b 15
ns
Note 1 During a burst A8–A15 are not TRI-STATE if byte wide transfers are selected On the last transfer A8–A15 are TRI-STATE as shown above
Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within bch a 15 ns enabling other devices to drive these
Obs ^{lines with no contention}
45