DP8390D Datasheet, PDF (34/58 Pages) National Semiconductor (TI) – NIC Network Interface Controller

13 0 Bus Arbitration and Timing
The NIC operates in three possible modes
te ^{Upon power-up the NIC is in an indeterminant state After}
receiving a Hardware Reset the NIC comes up as a slave in
the Reset State The receiver and transmitter are both dis-
abled in this state The reset state can be reentered under
three conditions soft reset (Stop Command) hard reset
(RESET input) or an error that shuts down the receiver or
le ^{transmitter (FIFO underflow or overflow) After initialization}
of registers the NIC is issued a Start command and the NIC
enters Idle state Until the DMA is required the NIC remains
in an idle state The idle state is exited by a request from the
FIFO in the case of receive or transmit or from the Remote
DMA in the case of Remote DMA operation After acquiring
the bus in a BREQ BACK handshake the Remote or Local
o ^{DMA transfer is completed and the NIC reenters the idle}
state
TL F 8582 – 64
DMA TRANSFERS TIMING
The DMA can be programmed for the following types of
transfers
16-Bit Address 8-bit Data Transfer
16-Bit Address 16-bit Data Transfer
32-Bit Address 8-bit Data Transfer
32-Bit Address 16-bit Data Transfer
All DMA transfers use BSCK for timing 16-Bit Address
modes require 4 BSCK cycles as shown below
Obs^{16-BitAddress 8-BitData}
TL F 8582 – 65
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