DAC5682Z_17 Datasheet, PDF (46/66 Pages) Texas Instruments – 16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)

DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
www.ti.com
8.6.11 Register Name: CONFIG10 – Address: 0x0A, Default = 0x00
7
0
DLL_delay(3:0):
6
5
DLL_delay(3:0)
0
0
4
3
2
1
0
DLL_invclk
DLL_ifixed(2:0)
0
0
0
0
0
The DCLKP/N LVDS input data clock has a DLL to automatically skew the clock to LVDS
data timing relationship, providing proper setup and hold times. DLL_delay(3:0) is used to
manually adjust the DLL delay ± from the fixed delay set by DLL_ifixed(2:0). Adjustment
amounts are approximate.
DLL_invclk:
DLL_ifixed(2:0):
DLL_delay(3:0)
Delay Adjust (degrees)
1000
50°
1001
55°
1010
60°
1011
65°
1100
70°
1101
75°
1110
80°
1111
85°
0000
90° (Default)
0001
95°
0010
100°
0011
105°
0100
110°
0101
115°
0110
120°
0111
125°
When set, used to invert an internal DLL clock to force convergence to a different solution.
This can be used in the case where the DLL delay adjustment has exceeded the limits of
its range.
Adjusts the DLL delay line bias current. Refer to the Electrical Characteristics table. Used
in conjunction with the DLL_invclk bit to select appropriate delay range for a given DCLK
frequency:
'011' – maximum bias current and minimum delay range
'000' – mid scale bias current
'101' – minimum bias current and maximum delay range
'100' – do not use.
46
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