DAC5682Z_17 Datasheet, PDF (28/66 Pages) Texas Instruments – 16-Bit, 1.0 GSPS 2x-4x Interpolating Dual-Channel Digital-to-Analog Converter (DAC)

DAC5682Z
SLLS853F – AUGUST 2007 – REVISED JANUARY 2015
www.ti.com
8.3.10 DAC Transfer Function
The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output
current up to 20 mA. Differential current switches direct the current to either one of the complementary output
nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output
currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-
chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a
factor of two.
The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage
reference source (+1.2 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to
provide a maximum full-scale output current equal to 16 times I_BIAS.
The relation between IOUT1 and IOUT2 can be expressed as:
IOUT1 = – IOUT_FS – IOUT2
(4)
We will denote current flowing into a node as – current and current flowing out of a node as + current. Because
the output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The
output current flow in each pin driving a resistive load can be expressed as:
IOUT1 = IOUT_FS × (65536 – CODE) / 65536
(5)
IOUT2 = IOUT_FS × CODE / 65536
(6)
where CODE is the decimal representation of the DAC data input word.
For the case where IOUT1 and IOUT2 drive resistor loads R_L directly, this translates into single ended voltages
at IOUT1 and IOUT2:
VOUT1 = AVDD – | IOUT1 | × R_L
(7)
VOUT2 = AVDD – | IOUT2 | × R_L
(8)
Assuming that the data is full scale (65536 in offset binary notation) and the R_L is 25 Ω, the differential voltage
between pins IOUT1 and IOUT2 can be expressed as:
VOUT1 = AVDD – | –0 mA | × 25 Ω = 3.3 V
(9)
VOUT2 = AVDD – | –20 mA | × 25 Ω = 2.8 V
(10)
VDIFF = VOUT1 – VOUT2 = 0.5 V
(11)
Do not exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal
distortion.
8.3.11 DAC Output SINC Response
Due to sampled nature of a high-speed DAC, the well known sin(x)/x (or SINC) response can significantly
attenuate higher frequency output signals. See the Figure 37 which shows the unitized SINC attenuation roll-off
with respect to the final DAC sample rate in 4 Nyquist zones. For example, if the final DAC sample rate F_S = 1.0
GSPS, then a tone at 440MHz is attenuated by 3.0dB. Although the SINC response can create challenges in
frequency planning, one side benefit is the natural attenuation of Nyquist images. The increased over-sampling
ratio of the input data provided by the 2x and 4x digital interpolation modes of the DAC5682Z improve the SINC
roll-off (droop) within the band of interest of the original signal.
28
Submit Documentation Feedback
Product Folder Links: DAC5682Z
Copyright © 2007–2015, Texas Instruments Incorporated