ADS8353 Datasheet, PDF (46/71 Pages) Texas Instruments – Simultaneous-Sampling, Analog-to-Digital Converters

ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
www.ti.com
As shown in Figure 96, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0
(CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have
at least 48 SCLK falling edges.
After exiting the STANDBY mode, a delay of t_{PU_STDBY} must elapse for the internal circuits to fully power-up and
resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the
CFR.B[11:6] bits programmed during frame (F+3).
Frame (F+2)
Frame (F+3)
Device exits
STANDBY mode
Frame (F+4)
Device in
STANDBY
CS
mode
tPU_STDBY
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48
SDO-A
and
SDO-B
SDI
CFG.B[15:12] = 1000b
These bits set device
configuration for Frame (F+4)
CFG.B[5] = 0
CFG.B[11:6]
CFG.B[4:0] = 00000b
Note that N is a function of the device configuration, as described in Table 4.
Figure 96. Exit STANDBY Mode
12
15 16
N
Valid Data as per device configuration
CFG settings for Frame (F+5)
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
46
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: ADS8353 ADS7853 ADS7253