ADS8353 Datasheet, PDF (41/71 Pages) Texas Instruments – Simultaneous-Sampling, Analog-to-Digital Converters

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ADS8353, ADS7853, ADS7253
SBAS584B – OCTOBER 2013 – REVISED AUGUST 2014
8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion
results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect
(NC) pin.
This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 92 shows a detailed timing diagram
for this mode.
Sample
N
t_CONV
t_THROUGHPUT
t_ACQ
Sample
N+1
CS
SCLK
12
14 15 16 17 18
28 29 30 31 32 33 34 44 45 46 47 48
ADS8353, ADS8354
SDO_A
ADS7853, ADS7854
SDO_A
ADS7253, ADS7254
SDO_A
All Devices
SDO_B
D1 D1
5-A 4-A
D1 D1
3-A 2-A
D1 D1
1-A 0-A
D4- D3- D2- D1- D0- D1
A A A A A 5-B
Data From Sample N
D2- D1- D0-
AAA
0
0
D1
3-B
Data From Sample N
D0-
A
0
0
0
Data From Sample N
0
D1
1-B
D4- D3- D2- D1- D0-
BBBBB
D2- D1- D0-
BBB
0
0
D0-
B
0
0
0
0
SDI
B15
B14 B3 B2 B1 B0 X X
XXXXXX
XXXX
X
Figure 92. 32-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device
converts the sampled analog input during the conversion time (t_CONV). SDO_A reads 0 during this period. After
competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs
the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are
used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin,
as shown in Table 14.
DEVICE PIN
ADS8353
ADS7853
ADS7253
SDO-A
SDO-A
SDO-A
CS
↓ ↓1
00
00
00
Table 14. Data Launch Edge
LAUNCH EDGE
SCLK
CS
— ↓15 ↓16
— ↓27 ↓28 ↓29 ↓30 ↓31 ↓32
— ↓43 ↓44 ↓45 ↓46 ↓47 ↓48 ... ↑
—
0 D15_A — D4_A D3_A D2_A D1_A D0_A D15_B — D4_B D3_B D2_B D1_B D0_B 0 ... Hi-Z
—
0 D13_A — D2_A D1_A D0_A 0
00
— D2_B D1_B D0_B 0
0
0 ... Hi-Z
—
0 D11_A — D0_A 0
0
0
00
— D0_B 0
0
0
0
0 ... Hi-Z
In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
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