ADC08DL500_14 Datasheet, PDF (46/57 Pages) Texas Instruments – ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter

ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
www.ti.com
Signal
50:
Input with
dc-coupled
50:
output
impedance
3.3V
LMH6555
R_F1
R_G1
-
+
R_G2
R_F2
V_{CM_REF}
R_T2
50:
R_T1
50:
V_IN-
V_IN+
LMV321
V_CMO
Figure 13. Example of Servoing the Analog Input with V_CMO
In Figure 13, R_ADJ-and R_ADJ+ are used to adjust the differential offset that can be measured at the ADC inputs
V_IN+ / V_IN-with LMH6555's input terminated to ground as shown but not driven and with no R_ADJ resistors applied.
An unadjusted positive offset with reference to V_IN-greater than |15mV| should be reduced with a resistor in the
R_ADJ-position. Likewise, an unadjusted negative offset with reference to V_IN-greater than |15mV| should be
reduced with a resistor in the R_ADJ+ position. Table 19 gives suggested R_ADJ-and R_ADJ+ values for various
unadjusted differential offsets to bring the V_IN+ / V_IN-offset back to within |15mV|.
Table 19. D.C. Coupled Offset Adjustment
Unadjusted Offset Reading
0mV to 10mV
11mV to 30mV
31mV to 50mV
51mV to 70mV
71mV to 90mV
91mV to 110mV
Resistor Value
no resistor needed
20.0kΩ
10.0kΩ
6.81kΩ
4.75kΩ
3.92kΩ
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and OR-
goes low. This output is active as long as accurate data on either or both of the buses would be outside the
range of 00h to FFh. Note that when the device is programmed to provide a second DCLK output, the OR
signals become DCLK2. Refer to REGISTER DESCRIPTION
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by the value of the ADC's reference voltage. The
reference voltage of the ADC08DL500 is derived from an internal band-gap reference. The FSR pin controls the
effective reference voltage of the ADC08DL500 such that the differential full-scale input range at the analog
inputs is a normal amplitude with the FSR pin high, or a reduced amplitude with FSR pin low as defined by the
specification V_IN in the Converter Electrical Characteristics. Best SNR is obtained with FSR high, but better
distortion and SFDR are obtained with the FSR pin low. The LMH6555 of is Figure 13 suitable for any Full Scale
Range.
2.3 THE CLOCK INPUTS
The ADC08DL500 has differential LVDS clock inputs, CLK+ and CLK−, which must be driven with an a.c.
coupled, differential clock signal. Although the ADC08DL500 is tested and its performance is guaranteed with a
differential 1 GHz clock, it typically will function well with input clock frequencies indicated in the Converter
Electrical Characteristics. The clock inputs are internally terminated and biased. The input clock signal must be
capacitively coupled to the clock pins as indicated in Figure 14.
46
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