ADC08DL500_14 Datasheet, PDF (40/57 Pages) Texas Instruments – ADC08DL500 Low Power, 8-Bit, Dual 500 MSPS A/D Converter

ADC08DL500
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Table 13. Q-Channel Full-Scale Voltage Adjust ⁽¹⁾
Addr: Bh (1011b)
(1) Only the end points of the range, not the full sweep, are tested in production test.
D15
D14
D13
D12
D11
D10
(MSB)
Adjust Value
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Write only (0x807F)
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
1
1
1
1
1
1
Bits 15:7
Bits 6:0
Full Scale Voltage Adjust Value. The input full-scale voltage or gain of the I-Channel ADC is adjusted linearly
and monotonically with a 9 bit data value. The adjustment range is ±20% of the nominal 700 mV_P-P differential
value.
0000 0000 0
560 mV_P-P
1000 0000 0
700 mV_P-P
1111 1111 1
840 mV_P-P
For best performance, it is recommended that the value in this field be limited to the range of 0110 0000 0b to
1110 0000 0b. i.e., limit the amount of adjustment to ±15%. The remaining ±5% headroom allows for the ADC's
own full scale variation. A gain adjustment does not require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Table 14. Sample Clock Phase Fine Adjust ⁽¹⁾
Addr: 1110
(1) Coarse and intermediate step size are tested in major steps only in production test; fine step size is not tested.
Write only (0x00FF)
D15
D14
D13
D12
D11
D10
D9
(MSB)
Fine Phase Adjust
D8
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
Bits 15:8
Bits 7:0
Fine Phase Adjust. The phase of the ADC sampling clock is adjusted monotonically by the value in this field.
00h provides a nominal zero phase adjustment, while FFh provides a nominal 50 ps of delay. Thus, each code
step provides approximately 0.2 ps of delay.
POR State: 0000 0000b
Must be set to 1b
Table 15. Sample Clock Phase Intermediate/Coarse Adjust ⁽¹⁾
Addr: Fh (1111b)
(1) Coarse and intermediate step size are tested in major steps only in production test; fine step size is not tested.
Write only (0x007F)
D15
D14
D13
D12
D11
D10
POL
(MSB) Coarse Phase Adjust
D9
D8
IPA
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
1
1
1
1
1
1
Bit 15
Bits 14:10
Polarity Select. When this bit is selected, the polarity of the ADC sampling clock is inverted.
POR State: 0b
Coarse Phase Adjust. Each code value in this field delays the sample clock by approximately 65 ps. A value of
00000b in this field causes zero adjustment.
POR State: 00000b
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