TMS470MF04207_16 Datasheet, PDF (45/68 Pages) Texas Instruments – TMS470MF04207/TMS470MF03107 16/32-Bit RISC Flash Microcontroller

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TMS470MF04207
TMS470MF03107
SPNS159C – JANUARY 2012
Table 5-9. Switching Characteristics Over Recommended Operating Conditions for Clocks^{(1)(2)(3)(4)(5)}
PARAMETER
TEST CONDITIONS⁽⁶⁾
MIN
MAX
UNIT
f_(HCLK)
System clock frequency
Pipeline mode enabled
Pipeline mode disabled, 0
flash wait states
80
MHz
28
f_(PROG/ERASE)
System clock frequency Flash
programming/erase
80
MHz
f_(VCLK/VCLK2)
f_(ECLK)
Peripheral VBUS clock frequency
External clock output frequency for ECP
Module
f_(HCLK)
20
MHz
MHz
f_(RCLK)
RCLK - Frequency out of PLL macro into
R-divider (Post ODPLL divider)
145
MHz
Pipeline mode enabled
12.50
t_c(HCLK)
Cycle time, system clock
Pipeline mode disabled, 0
flash wait states
35.71
ns
t_{c(PROG/ERASE)}
Cycle time, system clock - Flash
programming/erase
12.50
ns
t_{c(VCLK/VCLK2)}
t_c(ECLK)
t_c(RCLK)
Cycle time, peripheral clock
Cycle time, ECP module external clock output
Cycle time, RCLK minimum input cycle time
out of PLL macro into R-divider
t_c(HCLK)
ns
50.0
ns
6.90
ns
(1) f_(HCLK) = f_(OSC) / NR *NF /ODPLL/PLLDIV; for details, see the PLL documentation. TI strongly recommends selection of NR and NF
parameters such that NF ≤ 120 and (f_(OSC) / NR *NF) ≤ 400.
f_(VCLK) = f_(HCLK) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the peripheral VBUS clock divider ratio determined by the
VCLKR[3:0] bits in the SYS module.
(2) Enabling FM mode can reduce maximum rated operating frequencies. The degree of impact is application-specific and the specific
settings, as well as the impact of the settings, should be discussed and agreed upon prior to using FM modes. Use of FM modes do not
impact the maximum rated external clock output, f_(ECLK), for the ECP module.
(3) Pipeline mode enabled or disabled is determined by FRDCNTL[2:0].
(4) f_(ECLK) = f_(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the ECP
module.
(5) ECLK output will increase radiated emissions within the system that is used. Rated emissions at the device level do not include
emissions due to ECLK output.
(6) All test conditions assume FM Mode disabled and RAM ECC enabled with 0 waitstates for RAM.
RAM
Address Waitstates
Data Waitstates
Flash
Address Waitstates
Data Waitstates
0MHz
0MHz
0MHz
0MHz
0
0
0
0
1
28MHz
Figure 5-6. Timing - Wait States
56MHz
f(HCLK)
f(HCLK)
f(HCLK)
2
f(HCLK)
NOTE
If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the
maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not
exceeded. The speed of the device clocks may need be derated to accommodate the
modulation depth when FMzPLL frequency modulation is enabled.
Copyright © 2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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